JP2013077869A - Time-digital converter and pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TDC in which resolution of decimal frequency division, that is resolution of a phase, does not depend on one cycle of an output signal outputted by an oscillator.SOLUTION: A TDC 2 has: a plurality of delay elements 21 connected in series and having an input end to which an output signal CKV outputted by an oscillator is inputted; a plurality of latch circuits 22 respectively latching a plurality of delay clock signals outputted by the plurality of delay elements 21 at an edge timing of a reference signal FREF received by a PLL circuit; and a delay time adjustment circuit 32 adjusting a delay time of the plurality of delay elements 21 so that an edge timing of the output signal CKV inputted to the input end of the plurality of delay elements 21 connected in series and an edge timing of an output digital signal outputted from an output end of the plurality of delay elements 21 connected in series are synchronized.

Description

  The present invention relates to a time-digital converter applied to a PLL (Phase-Locked Loop) circuit that outputs a signal of a desired frequency based on a reference signal.

  A PLL circuit is used in a frequency synthesizer or a clock generation circuit of a wireless communication circuit. In recent years, an all-digital PLL (ADPLL) circuit that can operate at a low power supply voltage and can reduce the chip size has been studied (see, for example, Non-Patent Document 1).

The ADPLL circuit measures a phase difference between the input reference signal and the oscillator output signal, generates a digital value corresponding to an integer part and a decimal part of the frequency division number, and generates the digital value of the oscillator output signal using the generated digital value. The frequency is controlled so that the ratio between the frequency of the oscillator output signal and the frequency of the reference signal becomes a set frequency division number. A TDC (Time-to-Digital Converter) generates a digital value corresponding to the fractional part of the frequency division number. This operation will be described below.

  A configuration of a conventional TDC is shown in FIG. The TDC 2 includes a plurality of delay elements 21, a plurality of latch circuits 22, and a digital code generator 23.

  The plurality of delay elements 21 are connected in series and receive an output signal CKV output from the oscillator at the input end. The plurality of latch circuits 22 latch the plurality of delayed clock signals output from the plurality of delay elements 21 at the edge timing of the reference signal FREF to which the ADPLL circuit is input, respectively. The digital code generator 23 codes a plurality of latch output signals output from the plurality of latch circuits 22 to generate a digital code Dout indicating the relative time relationship of the output signal CKV with respect to the edge timing of the reference signal FREF. To do.

“ALL-DIGITAL FREQUENCY SYNTHEZSIZER in DEEP-SUBMICRON CMOS” Robert Bogdan Stanzewski / Poras T. By Balsara

  The resolution of fractional division, that is, the resolution of the phase is determined by how many delay times of one delay element 21 are included in one cycle of the output signal CKV. However, the delay time of one delay element 21 takes a certain time. Therefore, if one cycle of the output signal CKV is different, the number of stages of the delay elements 21 to be used is different, and the resolution of fractional division, that is, the resolution of the phase is different.

  Therefore, in order to solve the above-described problem, an object of the present invention is to provide a TDC in which the resolution of fractional division, that is, the resolution of the phase does not depend on one period of the output signal output from the oscillator.

  To achieve the above object, one delay element according to one period of the output signal output from the oscillator so that the delay time of the plurality of delay elements is equal to one period of the output signal output from the oscillator. Each delay time was adjusted.

  The present invention provides a plurality of delay elements connected in series and input with a clock signal at an input end, and a plurality of delay clock signals output from the plurality of delay elements, each latched at an edge timing of a reference digital signal. A digital code for generating a digital code indicating a relative time relationship of the clock signal with respect to an edge timing of the reference digital signal by coding a latch circuit and a plurality of latch output signals output from the plurality of latch circuits The generator, the clock signal input at the input terminals of the plurality of delay elements connected in series, and the output digital signal output at the output terminals of the plurality of delay elements connected in series have the same edge timing. A delay time adjusting circuit for adjusting the delay times of the plurality of delay elements. Time and wherein - is a digital converter.

  According to this configuration, it is possible to provide a time-digital converter in which the resolution of the fractional division, that is, the phase resolution does not depend on one period of the output signal output from the oscillator. In addition, if a general clock signal and a general reference digital signal are employed in place of the output signal output from the oscillator and the reference signal input to the PLL circuit, the time-digital converter of the present invention is replaced with the PLL circuit. It can be applied to other circuit configurations.

  Further, according to the present invention, the delay time adjustment circuit includes: the clock signal input at input terminals of the plurality of delay elements connected in series; and the plurality of delay clock signals output from the plurality of delay elements. Any one of the time-digital converters is characterized in that the delay times of the plurality of delay elements are adjusted so that the edge timings are equal.

  According to this configuration, the resolution of the fractional division, that is, the phase resolution can be made variable by changing the number of delay elements involved in the fractional division measurement, that is, the phase measurement. In addition, if a general clock signal and a general reference digital signal are employed in place of the output signal output from the oscillator and the reference signal input to the PLL circuit, the time-digital converter of the present invention is replaced with the PLL circuit. It can be applied to other circuit configurations.

  Further, the present invention provides an oscillator that outputs the output signal such that a phase difference between a reference signal and an output signal is 0, the clock signal as the clock signal, the output signal as input, and the reference digital signal as the reference signal. A time-to-digital converter that receives a reference signal and a phase comparator that outputs information indicating the phase difference based on a digital code indicating a relative time relationship of the output signal with respect to an edge timing of the reference signal And a PLL circuit characterized by comprising:

  According to this configuration, it is possible to provide a PLL circuit in which the fractional frequency resolution, that is, the phase resolution does not depend on one cycle of the output signal output from the oscillator.

  The present invention can provide a TDC in which the resolution of fractional division, that is, the phase resolution does not depend on one period of the output signal output from the oscillator.

It is a figure which shows the structure of TDC of a prior art. It is a figure which shows the structure of a PLL circuit. 1 is a diagram illustrating a configuration of a TDC according to Embodiment 1. FIG. It is a figure which shows the structure of TDC of Embodiment 2. FIG.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

(Outline of PLL circuit)
The configuration of the PLL circuit is shown in FIG. The PLL circuit P includes a DCO 1, a TDC 2, a sampler 3, a reference phase accumulator 4, a multiplier 5, a variable phase accumulator 6, a sampler 7, a phase detector 8, a loop filter 9, and a gain normalization circuit 10.

  The DCO 1 has a varactor (variable capacitance diode) array and controls the oscillation frequency with a binary code. The TDC2 measures the difference between the pulse edges of the output signal CKV of the DCO1 and the reference signal FREF as a time interval. The output value is a digital value corresponding to the fractional part circumference.

  The sampler 3 synchronizes the rising edge of the reference signal FREF with the rising edge of the output signal CKV of the DCO 1 and outputs the retimed reference signal CKR. The entire system operates in synchronization with the reference signal CKR. For example, the reference phase accumulator 4 and the sampler 7 synchronize the data update timing based on the reference signal CKR.

  The reference phase accumulator 4 accumulates the divided data FCW at the timing of the reference signal CKR and outputs it to the phase detector 8. The multiplier 5 multiplies a normalization coefficient for adjusting the DCO frequency division period in the DCO 1 and the output period of the TDC 2.

  The variable phase accumulator 6 counts up by +1 for each rising edge of the output signal CKV of the DCO 1 and outputs the digital value. The sampler 7 outputs the output value from the variable phase accumulator 6 to the phase detector 8 at the rising edge of the reference signal CKR. That is, the number of pulses of the output signal CKV of the DCO 1 in the cycle of the reference signal CKR is measured. This is digital data corresponding to integer division.

  The phase detector 8 compares the output value of the reference phase accumulator 4, the output value of the multiplier 5, and the output value of the sampler 7 by calculation, and outputs the result as a phase error to the loop filter 9. The output of the loop filter 9 is input to the gain normalization circuit 10. The gain normalization circuit 10 outputs a binary code for controlling the oscillation frequency to the DCO 1 based on the output of the loop filter 9.

(Embodiment 1)
The configuration of the TDC of Embodiment 1 is shown in FIG. The TDC 2 includes a plurality of delay elements 21, a plurality of latch circuits 22, a digital code generator 23, D-flip flop circuits 24 and 25, a NAND circuit 26, NOT circuits 27 and 28, D-flip flop circuits 29 and 30, and a delay. / Advance determination unit 31 and delay time adjustment circuit 32.

  The plurality of delay elements 21 are connected in series and receive the output signal CKV of the DCO 1 at the input end. The plurality of latch circuits 22 latch the plurality of delayed clock signals output from the plurality of delay elements 21 at the edge timing of the reference signal FREF, respectively. The digital code generator 23 codes a plurality of latch output signals output from the plurality of latch circuits 22 to thereby indicate a relative time relationship of the output signal CKV of the DCO 1 with respect to the edge timing of the reference signal FREF. Is generated.

  The delay time adjustment circuit 32 has an output signal CKV input at the input ends of the plurality of delay elements 21 connected in series and an output digital signal output at the output ends of the plurality of delay elements 21 connected in series as edges. The delay times of the plurality of delay elements 21 are adjusted so that the timings are equal. In other words, the delay time adjustment circuit 32 has a delay time of 1 for the output signal CKV output from the DCO 1 so that the delay time of the entire delay elements 21 is equal to one cycle of the output signal CKV output from the DCO 1. The delay time of each delay element 21 is adjusted.

  The delay / advance determination unit 31 includes an edge timing of the output signal CKV input at the input ends of the plurality of delay elements 21 connected in series and an output digital output at the output ends of the plurality of delay elements 21 connected in series. The result of comparison with the signal edge timing is output to the delay time adjustment circuit 32. The delay time adjustment circuit 32 executes the above-described processing based on the comparison result.

  The D-flip-flop circuit 24 receives an output signal CKV input at the input terminals of a plurality of delay elements 21 connected in series at the C terminal, inputs '1' at the D terminal, The latch result is output, and the output of the NAND circuit 26 described later is input at the R terminal. Note that the R terminal is low active.

  The D flip-flop circuit 25 inputs an output digital signal output from the output terminals of a plurality of delay elements 21 connected in series at the C terminal, inputs '1' at the D terminal, The latch result is output, and the output of the NAND circuit 26 described later is input at the R terminal. Note that the R terminal is low active.

  The NAND circuit 26 inputs the outputs of the D-flip flop circuits 24 and 25 and outputs a logical product of these outputs to the R terminals of the D-flip flop circuits 24 and 25.

  The D-flip flop circuit 29 receives a signal obtained by inverting the output of the D-flip flop circuit 24 by the NOT circuit 27 at the C terminal, and inputs the output of the D-flip flop circuit 25 at the D terminal. The latch result is output to the delay / advance determination unit 31 at the terminal.

  The D-flip flop circuit 30 receives a signal obtained by inverting the output of the D-flip flop circuit 25 at the C terminal by the NOT circuit 28, and inputs the output of the D-flip flop circuit 24 at the D terminal. The latch result is output to the delay / advance determination unit 31 at the terminal.

  The edge timing of the output signal CKV input at the input ends of the plurality of delay elements 21 connected in series is equal to the edge timing of the output digital signal output at the output ends of the plurality of delay elements 21 connected in series. Think about when. The outputs of the D-flip flop circuits 24 and 25 are pulse signals, while the outputs of the D-flip flop circuits 29 and 30 are continuous signals. The lag / advance determiner 31 receives the outputs of the D-flip flop circuits 29 and 30 rather than the outputs of the D-flip flop circuits 24 and 25 in order to obtain the edge timing comparison result correctly. desirable.

  In the first embodiment, it is possible to provide the TDC 2 in which the fractional frequency resolution, that is, the phase resolution does not depend on one cycle of the output signal CKV output from the DCO 1. If a general clock signal and a general reference digital signal are employed instead of the output signal CKV output from the DCO 1 and the reference signal FREF to which the PLL circuit P is input, the TDC 2 is replaced with a circuit other than the PLL circuit P. It can also be applied to configurations.

(Embodiment 2)
FIG. 4 shows the configuration of the TDC according to the second embodiment. The TDC 2 includes a plurality of delay elements 21, a plurality of latch circuits 22, a digital code generator 23, D-flip flop circuits 24 and 25, a NAND circuit 26, NOT circuits 27 and 28, D-flip flop circuits 29 and 30, and a delay. / Advance determination unit 31, delay time adjustment circuit 32 and selector 33.

  The delay time adjustment circuit 32 is configured so that one of the output signal CKV input at the input terminals of the plurality of delay elements 21 connected in series and the plurality of delay clock signals output from the plurality of delay elements 21 has an edge timing. The delay times of the plurality of delay elements 21 are adjusted so as to be equal. For this purpose, the selector 33 selects one of the outputs of the delay elements 21 and outputs the output of the selected delay element 21 to the C terminal of the D-flip flop circuit 25. Other configurations and processes are the same as those in the first and second embodiments.

  In the second embodiment, the resolution of the fractional division, that is, the phase resolution can be made variable by changing the number of delay elements 21 involved in the fractional division measurement, that is, the phase measurement. If a general clock signal and a general reference digital signal are employed instead of the output signal CKV output from the DCO 1 and the reference signal FREF to which the PLL circuit P is input, the TDC 2 is replaced with a circuit other than the PLL circuit P. It can also be applied to configurations.

  In the first and second embodiments, the R terminals of the D-flip flop circuits 24 and 25 are set low active. However, if the NAND circuit 26 is replaced with an AND circuit, the R terminal is high active. May be used.

  The TDC according to the present invention can be applied to a PLL circuit, and instead of the output signal CKV output from the DCO and the reference signal FREF to which the PLL circuit is input, a general clock signal and a general reference digital signal are respectively employed. For example, the present invention can be applied to circuit configurations other than the PLL circuit.

P: PLL circuit 1: DCO
2: TDC
3: Sampler 4: Reference phase accumulator 5: Multiplier 6: Variable phase accumulator 7: Sampler 8: Phase detector 9: Loop filter 10: Gain normalization circuit 21: Delay element 22: Latch circuit 23: Digital code generator 24 25: D-flip flop circuit 26: NAND circuit 27, 28: NOT circuit 29, 30: D-flip flop circuit 31: Delay / advance determination unit 32: Delay time adjustment circuit 33: Selector

Claims (3)

A plurality of delay elements connected in series and input with a clock signal at the input end;
A plurality of latch circuits for latching a plurality of delayed clock signals output by the plurality of delay elements at an edge timing of a reference digital signal;
A digital code generator for generating a digital code indicating a relative time relationship of the clock signal with respect to an edge timing of the reference digital signal by coding a plurality of latch output signals output by the plurality of latch circuits;
The clock signal input at the input ends of the plurality of delay elements connected in series and the output digital signal output at the output ends of the plurality of delay elements connected in series are equalized in edge timing. A delay time adjusting circuit for adjusting a delay time of the plurality of delay elements;
A time-to-digital converter.   The delay time adjustment circuit is configured such that one of the clock signal input at the input ends of the plurality of delay elements connected in series and the plurality of delay clock signals output from the plurality of delay elements is edge timing. The time-digital converter according to claim 1, wherein delay times of the plurality of delay elements are adjusted so as to be equal to each other. An oscillator that outputs the output signal such that the phase difference between the reference signal and the output signal is zero;
The time-digital converter according to claim 1 or 2, wherein the output signal is input as the clock signal, and the reference signal is input as the reference digital signal.
A phase comparator that outputs information indicating the phase difference based on a digital code indicating a relative time relationship of the output signal with respect to an edge timing of the reference signal;
A PLL circuit comprising: