JP2010273185A - Digital phase locked loop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem in a conventional digital phase locked loop circuit: a stable phase synchronization loop cannot be formed. <P>SOLUTION: A digital phase locked loop circuit includes: first and second counters for counting first and second clock signals, respectively; a delay clock-generating circuit for generating first and second delay clock signals delaying the first clock signal; a sampling circuit for sampling a count value of the second counter by the first clock signal and the first and second delay clock signals; a selecting circuit for selecting one of the sampled count values according to a phase difference from a third clock signal obtained by frequency-dividing the first and second clock signals by a predetermined number, and the sampled count values; a phase error-calculating circuit for calculating the phase difference from the first and third clocks according to the count values selected by the first counter and the selecting circuit; and a digital control oscillator for outputting a second clock according to the result of the calculation of the phase error-calculating circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a digital phase locked loop circuit.

  A conventionally known analog phase-locked loop (hereinafter referred to as analog PLL) 1 includes a phase frequency comparator 11, a charge pump 12, an analog filter 13, and a voltage controlled oscillator 14, as shown in FIG. , N frequency dividing circuit 15. Such an analog circuit such as the analog filter 13 is composed of analog elements such as resistors and capacitors, and an increase in circuit area becomes a problem. For this reason, analog PLLs are less likely to benefit from the miniaturization of CMOS technology, which is currently the mainstream in semiconductor circuits.

  The analog PLL is an analog signal for each cycle of the reference clock signal FREF and performs a phase comparison operation with the feedback clock signal FD. For this reason, there arises a problem that leakage of the input clock signal to the output clock signal due to frequency jump occurs. Furthermore, a problem of phase offset between input and output due to element variation or the like occurs. Therefore, a completely digital phase-locked loop (hereinafter referred to as AD (ALL Digital) PLL) in which the analog PLL is entirely replaced with a digital circuit configuration has been developed.

  The ADPLL does not require an analog element that increases the circuit area. Instead, it is composed of a digital circuit that performs digital signal processing. The digital circuit has an advantage that the circuit area can be reduced by miniaturization of CMOS technology. Further, since the phase comparison is also performed with digital data, the leakage of the input clock signal to the output clock signal due to the frequency jump does not occur unlike the analog PLL. In addition, accurate decimal point multiplication is possible. As an example of such ADPLL, there is a technique as disclosed in Patent Document 1.

  Here, FIG. 18 shows a block diagram of ADPLL2 as a conventional technique. ADPLL2 assumes that the analog PLL1 of FIG. 17 is digitized. As shown in FIG. 18, the ADPLL 2 includes counters 21 and 22, a TDC (Time-to-Digital Converter) circuit 23, a frequency dividing circuit 24, an adder 25, a phase error calculation circuit 26, and a digital filter 27. And a DCO (Digitally-Controlled-Oscillator) circuit 28.

  A portion related to the phase frequency comparator 11 and the charge pump 12 of the analog PLL 1 (UNIT 10 in FIG. 17) is a portion related to the counters 21 and 22 and the TDC circuit 23 and the adder 25 and the phase error calculation circuit 26 in the ADPLL 2 (UNIT 20 in FIG. 18). ). Similarly, the analog filter 13 corresponds to the digital filter 27. The voltage controlled oscillator 14 corresponds to the DCO circuit 28. The N frequency dividing circuit 15 corresponds to the frequency dividing circuit 24.

  In ADPLL2, the counter 21 counts the reference clock signal FREF and outputs it as a digital signal PFRC. The frequency dividing circuit 24 divides the output clock signal FOUT by N and outputs a feedback signal FD, and outputs a count value within N counts as the digital signal PFDC2. The counter 22 counts the feedback signal FD and outputs it as a digital signal PFDC. The adder 25 calculates the sum of the values of the digital signals PFDC1 and PFDC2 and outputs a digital signal PFDC. The TDC circuit 23 converts the phase difference (value after the decimal point) within one clock of the output clock signal FOUT into digital data, and outputs a digital signal PTDC and a polarity signal PTDC_SIGN indicating whether the phase difference is positive or negative.

  The phase error calculation circuit 26 calculates PFRC− (PFDC + PTDC) from the values of the digital signals PFRC, PFDC, and PTDC. A phase difference between the reference clock signal FREF and the feedback signal FD is output as a digital signal PERR from the calculation processing result and PTDC_SIGN. The digital filter 27 smoothes the digital signal PERR and outputs a digital signal DCON. The DCO circuit 28 outputs an output clock signal FOUT having a frequency corresponding to the digital signal DCON. The ADPLL2 operates so that the value of (| PFRC− (PFDC + PTDC) |) becomes “0”, and enters the locked state when it becomes “0”.

  Here, the relationship between the count values PFRC and PFDC will be described with reference to the graphs of FIGS. However, the counters 21 and 22 are assumed to be 4-bit counters (hexadecimal number counters). That is, 0-15 are counted. In addition, the time shown with the same code | symbol of FIGS. 19-21 shall point out the same time.

  First, the relationship between the reference clock signal FREF and the count value PFRC is shown in FIG. As shown in FIG. 19, the reference clock signal FREF rises at times t1, t3, t5, t7, and t9. Accordingly, the count value PFRC that is the phase data of the reference clock signal FREF is also output at times t1, t3, t5, t7, and t9.

  Next, the relationship between the feedback clock signal FD and the count value PFDC is shown in FIG. As shown in FIG. 20, the feedback clock signal FD rises at times t2, t4, t6, t8, and t10. Therefore, the count value PFDC1 that is the phase data of the feedback clock signal FD is also output at times t2, t4, t6, t8, and t10. Further, the frequency dividing circuit 24 outputs a count value PFDC2 every time the output clock signal FOUT is counted. Therefore, the adder 25 outputs a count value PFDC obtained by adding PFDC1 and PFDC2.

  Finally, it is the phase difference between the count value PFRC that is the phase data of the reference clock signal FREF and the count value PFDC that is the phase data of the feedback clock signal FD shown in the graphs of FIGS. 19 and 20 (| PFRC−PFDC | ) Is shown in the lowermost graph of FIG. As described above, the data of the value “4”, which is the phase difference between the reference clock signal FREF and the feedback signal FD, is calculated at the clock timing of the reference clock signal FREF having a cycle slower than that of the output clock signal FOUT.

  In FIG. 19 to FIG. 21, for simplification of description, the phase difference between the reference clock signal FREF and the feedback signal FD is always constant, and there is no phase difference within one clock of the output clock signal FOUT ( The case of PTDC = 0) is shown. However, as described above, since ADPLL2 operates so that the value of (| PFRC-PFDC |) becomes “0” as described above, it is calculated at times t3, t5, t7, and t9 (| PFRC-PFDC | ) Will decrease.

JP 2002-76886 A

  Here, the counter 21 and the TDC circuit 23 operate at the clock timing of the reference clock signal FREF, and the data is updated. Other circuits such as the counter 22 and the phase error calculation circuit 26 operate at the output clock signal FOUT and its divided clock timing, and data is updated. However, the reference clock signal FREF and the feedback signal FD have an asynchronous relationship. Therefore, the above-described digital count values PFRC and PFDC, which are phase data, also transition at different timings.

  Problems caused by this will be described with reference to FIGS. First, FIG. 22 shows a case where there is no problem in the phase data transition timing. As shown in FIG. 22, the digital data PFDC is taken into the phase error calculation circuit 26 in accordance with the rising edge of the reference clock signal FREF. Here, at the timing of the rising edge of the reference clock signal FREF, the value of the digital data PFDC is stably “9”. Therefore, the value used by the phase error calculation circuit 26 for the calculation can be “9”. Since the value of the digital data PFRC in this example is “10”, the value of the phase difference (| PFRC−PFDC |) is “1”.

  FIG. 23 shows a case where there is a problem in the phase data transition timing. As shown in FIG. 23, the digital data PFDC is taken into the phase error calculation circuit 26 in accordance with the rising edge of the reference clock signal FREF as in FIG. However, unlike the case of FIG. 22, at the timing of the rising edge of the reference clock signal FREF, the value of the digital data PFDC is in the transition process from “9” to “10”. The value “X” of the digital data PFDC in this transition process is an indefinite value. Therefore, the value “X” of the indefinite digital data PFDC is taken into the phase error calculation circuit 26 and used for calculation. For this reason, there arises a problem that the calculation result does not become an accurate value. In particular, this problem often occurs in the vicinity of the lock state in which the rising edges of the reference clock signal FREF and the feedback signal FD are to be synchronized.

  Thus, in order for ADPLL2 to operate reliably as a PLL, it is necessary to compare accurate and stable phase data PFRC and PFDC, respectively, at a predetermined time. However, as described above, when the phase data PFRC and PFDC are compared at a predetermined time, if one of the phase data is in a transition process, there is a problem that accurate phase data cannot be compared.

  The present invention provides a first counter that counts a first clock signal, a second counter that counts a second clock signal, and first and second delayed clocks in which the first clock signal is sequentially delayed. A delay clock generation circuit for generating a signal; a first sample circuit for sampling a count value of the second counter with each of the first clock signal and the first and second delay clock signals; and the first According to the phase difference between the first clock signal and the third clock signal obtained by dividing the second clock signal by a predetermined number, and the count value sampled by the first sample circuit. According to the selection circuit that selects one of the count values sampled by the sample circuit, the count value of the first counter, and the count value selected by the selection circuit A phase error calculation circuit that calculates a phase difference between the first clock and the third clock, and a digitally controlled oscillator that outputs the second clock according to the calculation result of the phase error calculation circuit It is a digital phase locked loop circuit.

  The digital phase-locked loop circuit according to the present invention samples the count value of the second counter with each of the first clock signal and the first and second delayed clock signals. The selection circuit selects one of the sampled count values according to the phase difference between the first and third clock signals and the count value sampled by the first sample circuit. For this reason, even if one of the sampled count values is indeterminate during the transition process, it is accurate from the relationship between the other sampled count values and the phase difference between the first and third clock signals. The count value can be selected by the selection circuit.

  The digital phase locked loop circuit according to the present invention can constitute a stable phase locked loop.

1 is a configuration of an ADPLL circuit according to an embodiment. 1 is a configuration of a TDC circuit according to an embodiment. 6 is a timing chart for explaining the operation of the TDC circuit according to the embodiment. 6 is a timing chart for explaining the operation of the TDC circuit according to the embodiment. 6 is a timing chart for explaining the operation of the TDC circuit according to the embodiment. 6 is a timing chart for explaining the operation of the PDF sample circuit according to the embodiment. 6 is a timing chart for explaining the operation of the PDF sample circuit according to the embodiment. 6 is a timing chart for explaining the operation of the PDF sample circuit according to the embodiment. 6 is a timing chart for explaining the operation of the PDF sample circuit according to the embodiment. 6 is a timing chart for explaining the operation of the PDF sample circuit according to the embodiment. 6 is a timing chart for explaining the operation of the PDF sample circuit according to the embodiment. 6 is a timing chart for explaining the operation of the PDF sample circuit according to the embodiment. It is a schematic diagram for demonstrating the principle of operation of the PDF selection circuit concerning embodiment. 5 is a table for explaining the operation principle of the PDF selection circuit according to the embodiment. It is the table | surface which put together the operation | movement result of the PDF selection circuit concerning Embodiment. 5 is a timing chart for explaining the operation of the ADPLL circuit according to the embodiment. This is a configuration of a conventional analog PLL circuit. This is a configuration of a conventional ADPLL circuit. It is a schematic diagram explaining operation | movement of the conventional ADPLL circuit. It is a schematic diagram explaining operation | movement of the conventional ADPLL circuit. It is a schematic diagram explaining operation | movement of the conventional ADPLL circuit. It is a timing chart for demonstrating operation | movement of the conventional ADPLL circuit. It is a timing chart for demonstrating the problem of the conventional ADPLL circuit.

  BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows an example of the configuration of a complete digital phase-locked loop (hereinafter referred to as ADPLL) circuit 100 according to the present embodiment. As shown in FIG. 1, the ADPLL circuit 100 includes counters 101 and 102, a time-to-digital converter (TDC) circuit 103, a frequency divider circuit 104, an adder circuit 105, a PFD sample circuit 106, and a PFDS selection. The circuit 107, the sampling circuit 108, the phase error calculation circuit 109, the digital filter 110, the DCO (Digitally-Controlled-Oscillator) circuit 111, the reference clock input terminal 112, and the output clock output terminal 113 are included.

  The reference clock input terminal 112 inputs a reference clock signal FREF (first clock signal).

  The counter 101 (first counter) counts the multiplication set value every time the reference clock signal FREF is input. For example, if the setting is multiplied by 10, the counter 101 counts up by 10 each time one clock of the reference clock signal FREF is input. Then, the count value PFRC is output to the sampling circuit 108. Note that the symbol “PFRC” indicates a count value and a digital count value signal name for storing the count value.

  The counter 102 (third counter) counts the feedback clock signal FD output from the frequency dividing circuit 104. Then, the count value PFDC1 is output to the adder circuit 105.

  The frequency dividing circuit 104 divides the output clock signal FOUT output from the DCO circuit 111 by a value equal to the multiplication set value and outputs the result. The clock divided to the predetermined value is set as a feedback clock signal FD. For example, when the frequency dividing circuit 104 has a function of dividing the input clock signal by 1/10, when the 100 MHz output clock signal FOUT is input, the feedback clock signal FD having a clock frequency of 10 MHz is output. Further, the frequency dividing circuit 104 counts the clock of the output clock signal FOUT within one cycle of the feedback clock signal FD described above. Then, the count value PFDC 2 is output to the adder circuit 105.

  Here, for example, consider a case where the frequency dividing circuit 104 has a function of dividing the input clock signal by 1/10. In this case, the counter 102 counts 1 every 10 clocks of the output clock signal FOUT, and outputs the count value as PFDC1. Then, the frequency dividing circuit 104 outputs the clock count values 0 to 9 of the output clock signal FOUT within one cycle of the feedback clock signal FD as the count value PFDC2. That is, in this example in which the frequency division is set to 10, the counter 102 counts 10 digits of the number of clocks of the output clock signal FOUT, and the frequency dividing circuit 104 counts 1 digit.

  The adder circuit 105 adds the count value PFDC1 from the counter 102 and the count value PFDC2 from the frequency divider circuit 104, and outputs the result to the PFD sample circuit 106 as the count value PFDC. The code “PFDC” indicates a count value and a digital count value signal name for storing the count value. Note that the relationship between the count values PFRC, PFDC1, PFDC2, and PFDC described above is the same as that described with reference to FIGS. Note that the counter 102, the frequency dividing circuit 104, and the adding circuit 105 constitute a second counter.

  The TDC circuit 103 (phase difference detector) measures the phase difference within one clock of the output clock FOUT between the reference clock signal FREF and the feedback clock signal FD that cannot be measured by the counters 101 and 102. Then, the value of the measurement result is normalized with the value of one period of digital data of the output clock signal FOUT. The normalization result is output as a phase difference detection signal PTDC of digital data. Further, as a result of normalization, a determination value as to whether or not the value of PTDC is greater than or equal to a predetermined value is added to the phase difference detection signal PTDC of the digital data. Further, the advance / delay of the phase of the feedback clock signal FD with respect to the phase of the reference clock signal FREF is output as a phase polarity signal PTDC_SIGN (polarity value). Further, the delayed clock signals FR1 and FR2 obtained by sequentially delaying the reference clock signal FREF for a predetermined period are output.

  FIG. 2 shows an example of the circuit configuration of the TDC circuit 103. As shown in FIG. 2, the TDC circuit 103 includes a plurality of flip-flop circuits, a plurality of delay elements, a plurality of inverters, a plurality of AND circuits, a comparison / selection circuit 201, a binary encoder 202, and a normalization. Circuit 203.

  The TDC circuit 103 has 2n + 2 delay elements (n: a positive integer). Among the plurality of delay elements, there are n + 1 delay elements that sequentially delay the feedback clock signal FD. These delay elements are denoted by BP1 to BPn + 1, respectively. The feedback clock signals FD sequentially delayed by the delay elements BP1 to BPn + 1 are denoted as FD1 to FDn + 1, respectively. In addition, among the plurality of delay elements, there are n + 1 delay elements that sequentially delay the reference clock signal FREF. These delay elements are denoted as BN1 to BNn + 1, respectively. The delay elements BN1 to BNn + 1 (delayed clock generation circuit) use the clock signals FREF sequentially delayed as clock signals FR1 to FRn + 1, respectively. The delay period of the delay elements BN1 to BNn + 1 is within a half cycle of the output clock signal FOUT and is equal to or longer than the transition time in which the value of the count value PFDC changes. Note that the delay elements BP1 to BPn + 1 and BN1 to BNn + 1 cause the same delay to the input signal. Hereinafter, the clock signals FD1 to FDn + 1 obtained by delaying the feedback clock signal FD and the clock signals FR1 to FRn + 1 obtained by delaying the reference clock signal FREF are referred to as delayed clock signals. The TDC circuit 103 outputs FR1 and FR2 among the delayed clock signals FR1 to FRn + 1 to the PFD sample circuit 106.

  Further, the TDC circuit 103 has 2n + 3 flip-flop circuits. Among the plurality of flip-flop circuits, the flip-flop circuits that input the delayed clock signals FD1 to FDn + 1 to the input data terminal and input the reference clock signal to the clock terminal are denoted as FFP1 to FFPn + 1, respectively. Further, among the plurality of flip-flop circuits, the flip-flop circuits that input the feedback clock signal FD to the input data terminal and input the delayed clock signals FR1 to FRn + 1 to the clock terminal are denoted as FFN1 to FFNn + 1, respectively. A flip-flop circuit that inputs a non-delayed feedback clock signal FD to the input data terminal and a non-delayed reference clock signal to the clock terminal is denoted as FF0.

  Signals output from the output data terminals of the flip-flop circuits FFN1 to FFNn + 1 are respectively output from PDN1 to PDNn + 1, signals output from the output data terminal of the flip-flop circuit FF0 are output from the output data terminals of PD0 and flip-flop circuits FFP1 to FFPn + 1. These signals are PDP1 to PDPn + 1, respectively. Hereinafter, these signals PDN1 to PDNn + 1 and PDP1 to PDPn + 1 are referred to as sampling signals.

  The TDC circuit 103 has 2n + 2 inverter elements. Among the plurality of inverter elements, inverter elements to which sampling signals PDN1 to PDNn are input are denoted as IVN1 to IVNn, respectively. The signals output from the inverter elements IVN1 to IVNn are referred to as PDNB1 to PDNBn, respectively. In addition, among the plurality of inverter elements, the inverter elements to which the sampling signals PDP1 to PDPn + 1 are input are referred to as IVP1 to IVPn + 1, respectively. The signals output from the inverter elements IVP1 to IVPn are referred to as PDNB1 to PDNBn, respectively. Further, an inverter element to which the signal PD0 is input is IV0, and a signal output from the inverter element IV0 is PDB0.

  The TDC circuit 103 has 2n + 2 AND circuits. Each AND circuit calculates a product of two inputs and outputs a calculation result. Of the plurality of AND circuits, n + 1 are ANDN1 to ANDNn + 1, and the remaining n + 1 are ANDP1 to ANDPn + 1.

  The AND circuit ANDN1 receives the sampling signal PDN1 and the signal PDB0 and outputs the calculation result as a signal NEG [n]. The AND circuit ANDN2 receives the sampling signal PDN2 and the signal PDNB1, and outputs the calculation result as a signal NEG [n−1]. The AND circuit ANDN3 receives the sampling signal PDN3 and the signal PDNB2, and outputs the calculation result as a signal NEG [n-2]. Thereafter, the same configuration is repeated, and finally, the AND circuit ANDNn + 1 receives the sampling signal PDNn + 1 and the signal PDNBn, and outputs the calculation result as a signal NEG [0].

  On the other hand, the AND circuit ANDP1 receives the sampling signal PD0 and the signal PDPB1, and outputs the calculation result as a signal POS [n]. The AND circuit ANDP2 receives the sampling signal PDP1 and the signal PDPB2, and outputs the calculation result as a signal POS [n−1]. The AND circuit ANDP3 receives the sampling signal PDP2 and the signal PDPB3, and outputs the calculation result as a signal POS [n-2]. Thereafter, the same configuration is repeated, and finally, the AND circuit ANDPn + 1 receives the sampling signal PDPn and the signal PDPBn + 1, and outputs the calculation result as the signal POS [0]. Hereinafter, the signals NEG [n] to NEG [0] and POS [n] to POS [0] are referred to as edge extraction signals.

  The comparison / selection circuit 201 converts the edge extraction signals NEG [n] to NEG [0] into a bus, the edge extraction signal NEG [n: 0] transmitted by the bus, and the edge extraction signals POS [n] to POS. [0] is converted into a bus, and an edge extraction signal POS [n: 0] transmitted by the bus is input. The comparison selection circuit 201 compares the edge extraction signal NEG [n: 0] with POS [n: 0]. As will be described later with reference to FIGS. 3 to 5, the signals NEG [n: 0] and POS [n: 0] are phase difference information of the rising edge of the feedback clock signal FD based on the rising edge of the reference clock signal FREF. have. By comparing this signal NEG [n: 0] with POS [n: 0], it is possible to determine the phase delay of the feedback clock signal FD with respect to the reference clock signal FREF. It is determined whether one of the edge extraction signals NEG [n: 0] and POS [n: 0] has a value of “1”. For example, when POS [n: 0] has “1”, the signal is high. The level phase polarity signal PTDC_SIGN is output, and the edge extraction signal POS [n: 0] is output as the signal TDC [n: 0]. Conversely, when the edge extraction signal NEG [n: 0] has a value of “1”, the low level signal PTDC_SIGN is output, and the edge extraction signal NEG [n: 0] is output as the signal TDC [n: 0]. To do.

  The binarization encoder 202 generates digital data in response to the signal TDC [n: 0] from the comparison / selection circuit 201. The normalization circuit 203 generates one cycle of the output clock signal FOUT from the output clock signal FOUT as digital data, and normalizes the value of the digital data generated by the binarization encoder 202 with the data value. Then, the normalized value is output as a phase difference detection signal PTDC of digital data. Note that the normalization circuit 203 generates digital data of one cycle of the output clock signal FOUT as the number of stages of delay elements that generate delays similar to the delay elements BP1 to BPn + 1. The value of the phase difference detection signal PTDC is digital data of a decimal value of 0 or more and 1 or less if the phase advance / delay of the feedback clock signal FD with respect to the reference clock signal FREF is one cycle or less of the output clock signal FOUT. Is output. Further, if the normalized result value (PTDC value) is smaller than 0.5, the normalization circuit 203 sets the most significant bit (MSB) of the phase difference detection signal PTDC of the digital data to “0”. If it is 5 or more, the MSB is “1”.

  For example, when the value of the digital data of one cycle of the output clock signal FOUT generated by the normalization circuit 203 is “10” and the value of the digital data of the binarization encoder 202 is “2”, the digital data after normalization The value is “0.2”. Therefore, the MSB of the digital data phase difference detection signal PTDC is “0” and the value is “0.2”. Similarly, if the value of the digital data of one cycle of the output clock signal FOUT generated by the normalization circuit 203 is “10” and the value of the digital data of the binary encoder 202 is “7”, the normalized digital data The value of “0.7” is “0.7”. Accordingly, the digital data phase difference detection signal PTDC has an MSB of “1” and a value of “0.7”.

  As described above, the TDC circuit 103 can output an error of one cycle or less of the output clock signal FOUT as the phase difference detection signal PTDC that stores digital data having a value after the decimal point. Further, based on the MSB value of the phase difference detection signal PTDC, it can be determined whether the phase difference of the phase of the feedback clock signal FD with respect to the reference clock signal FREF is larger or smaller than a half cycle of the output clock signal FOUT. Further, the phase polarity signal PTDC_SIGN can determine whether the phase of the feedback clock signal FD is delayed or advanced with respect to the reference clock signal FREF. However, the configuration of the TDC circuit 103 in FIG. 2 is an example, and may be realized by other circuit configurations as long as they have the same function.

  Hereinafter, the operation of the TDC circuit 103 will be briefly described. 3 to 5 are timing charts for explaining the operation of the TDC circuit 103. FIG. In FIG. 3, the phase of the feedback clock signal FD is delayed by a period T1 with respect to the phase of the reference clock signal FREF. As shown in FIG. 3, the reference clock signal FREF rises to a high level at time t1, but the rising edge of the feedback clock signal FD is delayed by a period T1 with respect to this rising edge. For this reason, all the sampling signals PDN1 to PNPn + 1, PD0, and PDP1 output by the flip-flops FFN1 to FFNn + 1, FF0, and FFP1 to FFPn + 1 even when the delayed clock signal FR1 rises to a high level at time t1 ˜PDPn + 1 is at the low level.

  At time t3, the feedback clock signal FD rises to a high level. Since the phase of the feedback clock signal FD is ahead of the delayed clock signal FR2, the sampling signal PDN2 rises to a high level in response to the rising edge of the delayed clock signal FR2 at time t4. Thereafter, the signals PDN3 to PDNn + 1 rise to a high level in response to the rising edges of the delayed clock signals FR3 to FRn + 1.

  Therefore, only the edge extraction signal NEG [n−1] rises to a high level at time t4, that is, the output value of the AND circuit ANDN2 becomes “1”. Further, the comparison / selection circuit 201 outputs the low-level phase polarity signal PTDC_SIGN and NEG [n: 0] as the signal TDC [n: 0] because NEG [n−1] has a value of “1”. The binarizing encoder 202 determines that the phase of the feedback clock signal FD is delayed by three stages with a delay element with respect to the phase of the reference clock signal FREF in accordance with the signal TDC [n: 0]. , “3” is output. The normalization circuit 203 normalizes this value and outputs it as a phase difference detection signal PTDC. The MSB of the phase difference detection signal PTDC is determined according to the value of one cycle of the output clock signal FOUT. For example, if the digital value for one period of the output clock signal FOUT is “10”, the normalized value is “0.3”, and therefore the phase difference detection signal PTDC is “0”. If the digital value for one period of the output clock signal FOUT is “5”, the value after normalization is “0.6”, so the MSB value of the phase difference detection signal PTDC is “1”. Hereinafter, the same applies to the MSB value of the phase difference detection signal PTDC in the description of FIGS.

  In FIG. 4, the rising edges of the reference clock signal FREF and the feedback clock signal FD rise to the high level almost simultaneously at time t1. In this case, the sampling signal PD0 rises to a high level at time t1. Thereafter, the signals PDN1 to PDNn + 1 rise to a high level in response to rising edges of the delayed clock signals FR1 to FRn + 1. On the other hand, all of the sampling signals PDP1 to PDPn + 1 are at a low level.

  For this reason, only the edge extraction signal POS [n] rises to a high level at time t1. That is, the output value of the AND circuit ANDP1 is “1”. Further, the comparison / selection circuit 201 outputs the high-level phase polarity signal PTDC_SIGN and POS [n: 0] as the signal TDC [n: 0] because POS [n] has a value of “1”. The binarization encoder 202 determines that the phase of the feedback clock signal FD has no delay with respect to the phase of the reference clock signal FREF according to the signal TDC [n: 0], and has a value of “1”. Is generated. The normalization circuit 203 normalizes this value and outputs it as a phase difference detection signal PTDC.

  In FIG. 5, the phase of the reference clock signal FREF is delayed by a period T2 with respect to the phase of the feedback clock signal FD. Therefore, even when the feedback clock signal FD at time t1 and the delayed clock signal FD1 rises to high level at time t2, the sampling signals PDN1, PD0, PDP1 to PDPn + 1 from the flip-flops FFN1 to FFNn + 1, FF0, FFP1 to FFPn + 1 are all Become low level. At time t3, the reference clock signal FREF rises to a high level. For this reason, at time t3, the respective sampling signals PD0 and PDP1 output from the flip-flops FF0 and FFP1 become high level. Thereafter, the signals PDN1 to PDNn + 1 rise to a high level in response to rising edges of the delayed clock signals FR1 to FRn + 1.

  For this reason, only the edge extraction signal POS [n−1] rises to a high level at time t3. That is, the output value of the AND circuit ANDP2 is “1”. Furthermore, since POS [n−1] has a value of “1”, the comparison / selection circuit 201 outputs the high-level phase polarity signal PTDC_SIGN and POS [n: 0] as the signal TDC [n: 0]. . The binarization encoder 202 determines that the phase of the feedback clock signal FD is advanced by two stages by the delay element with respect to the phase of the reference clock signal FREF in response to the signal TDC [n: 0]. Is generated. The normalization circuit 203 normalizes this value and outputs it as a phase difference detection signal PTDC.

  Note that the above-described NEG [n: 0] and POS [n: 0] are the first comparison result and the second comparison result. As described above, the TDC circuit 103 includes a circuit that uses the reference clock signal as the clock signal and the feedback clock signal FD as the data signal, and delays each signal. Then, the delayed reference clock signal and the feedback clock signal FD are respectively compared, and the phase difference of the feedback clock signal FD with respect to the reference clock signal and the phase Measure lag advance. Further, the phase difference is normalized by one period of the output clock signal FOUT.

  The PFD sample circuit 106 takes in the value of the count value PFDC from the adder circuit 105 at the timing of the rising edges of the reference clock signal FREF and the delayed clock signals FR1 and FR2. Then, the count values captured at the respective timings are output to the PFD selection circuit 107 as phase data signals PFDS0, PFDS1, and PFDS2. At the timing of the rising edge of the reference clock signal FREF, the acquired count value PFDC is the phase data signal PFDS0, and at the timing of the rising edge of the delayed clock signal FR1, the count value PFDC is acquired as the phase data signal PFDS1 and the delayed clock signal. The value of the count value PFDC captured at the timing of the rising edge of FR2 is set as the phase data signal PFDS2.

  Here, the values of the phase data signals PFDS0, PFDS1, and PFDS2 output from the PFD sample circuit 106 differ depending on the timing of the rising edge of the feedback clock signal FD and the reference clock signal FREF. 6 to 12 show the relationship between the values of the phase data signals PFDS0, PFDS1, and PFDS2 in accordance with the difference between the rising timing of the feedback clock signal FD and the timing of the rising edge of the reference clock signal FREF.

  FIG. 6 shows the delay amount from the reference clock signal FREF to the delayed clock signal FR1 as tdFR, and the delay amount from the reference clock signal FREF to the delayed clock signal FR2 as 2 × tdFR. Here, the feedback clock signal FD is inputted with the delay amount tdFR in order to prevent the count value PFDC fetched from the reference clock signal FREF and the delayed clock signals FR1 and FR2 by the PFD sample circuit 106 from becoming uncertain values. It is necessary to set a delay amount equal to or longer than the delay time tdFD until the PFDC value is determined after being set. Further, in order to avoid capturing the phase data signals PFDS0, PFDS1, and PFDS2 over two or more cycles of the output clock signal FOUT, 2 × tdFR is a delay within half of one cycle of the output clock signal FOUT (hereinafter referred to as tFO). It is assumed that the amount. Thus, the reason why 2 × tdFR is set to a delay amount within half of tFO is that the above-described phase difference detection signal PTDC is used when phase data is determined later. Ideally, tdFD << tdFR << 2 × tdFR << tFO (hereinafter referred to as conditional expression 1) needs to be satisfied. As a result, the data captured as the phase data signals PFDS0, PFDS1, and PFDS2 can take only three states: a determined adjacent data value or an indefinite value during the transition. However, in practice, there is a limit to reducing the delay of tdFD, and when the output clock signal FOUT becomes high speed, it becomes difficult to always satisfy the above-described conditional expression, and tdFD and tdFR are infinitely equal. Exists. In this embodiment, even in such a case, this problem is solved by performing processing for obtaining correct data as described below. In addition, although the above-mentioned description was performed based on FIG. 6, it is the same also in the case of FIGS.

  First, in FIG. 6, the reference clock signal FREF rises to a high level at time t1. The value PFDCn of the count value PFDC at the time t1 is output as the phase data signal PFDS0. At time t2, the delayed clock signal FR1 rises to a high level. The value PFDCn of the count value PFDC at time t2 is output as the phase data signal PFDS1. At time t3, the delayed clock signal FR2 rises to a high level. The value PFDCn of the count value PFDC at time t3 is output as the phase data signal PFDS2. Thereafter, the feedback clock signal FD rises, and at time t4, the count value PFDC changes from PFDCn to PFDCn + 1. However, the count value PFDC has been taken in before time t4, and all the values of the phase data signals PFDS0, PFDS1, and PFDS2 are the same value PFDCn. Therefore, PFDS0 = PFDS1 = PFDS2. Note that the symbols “PFDS0”, “PFDS1”, and “PFDS2” indicate the phase data signal name and the count value stored by the signal, respectively.

  In FIG. 7, the reference clock signal FREF rises to a high level at time t1. The value PFDCn of the count value PFDC at the time t1 is output as the phase data signal PFDS0. At time t2, the delayed clock signal FR1 rises to a high level. The value PFDCn of the count value PFDC at time t2 is output as the phase data signal PFDS1. Thereafter, the feedback clock signal FD rises, and at time t3, the count value PFDC changes from PFDCn to PFDCn + 1. At this time t3, the delayed clock signal FR2 rises to a high level. Therefore, the value of the count value PFDC output as the phase data signal PFDS2 is a transition state value and is output as an indefinite value.

  In FIG. 8, the reference clock signal FREF rises to a high level at time t1. The value PFDCn of the count value PFDC at the time t1 is output as the phase data signal PFDS0. At time t2, the delayed clock signal FR1 rises to a high level. The value PFDCn of the count value PFDC at time t2 is output as the phase data signal PFDS1. Thereafter, the feedback clock signal FD rises, and at time t3, the count value PFDC changes from PFDCn to PFDCn + 1. At time t4, the delayed clock signal FR2 rises to a high level. The value PFDCn + 1 of the count value PFDC at time t4 is output as the phase data signal PFDS2.

  Here, in the patterns of FIGS. 7 and 8, the values of the phase data signals PFDS0, PFDS1, and PFDS2 are PFDS0 = PFDS1 ≠ PFDS2.

  In FIG. 9, the reference clock signal FREF rises to a high level at time t1. The value PFDCn of the count value PFDC at the time t1 is output as the phase data signal PFDS0. Thereafter, the feedback clock signal FD rises, and the value of the count value PFDC transits from PFDCn to PFDCn + 1 at time t2. At this time t2, the delayed clock signal FR1 rises to a high level. For this reason, the value of the count value PFDC output as the phase data signal PFDS1 is a transition state value and is output as an indefinite value. At time t3, the delayed clock signal FR2 rises to a high level. The value PFDCn + 1 of the count value PFDC at time t3 is output as the phase data signal PFDS2. For this reason, the values of the phase data signals PFDS0, PFDS1, and PFDS2 are all different values. Therefore, PFDS0 ≠ PFDS1 ≠ PFDS2.

  In FIG. 10, the reference clock signal FREF rises to a high level at time t1. The value PFDCn of the count value PFDC at the time t1 is output as the phase data signal PFDS0. Thereafter, the feedback clock signal FD rises, and at time t2, the count value PFDC changes from PFDCn to PFDCn + 1. At time t3, the delayed clock signal FR1 rises to a high level. The value PFDCn + 1 of the count value PFDC at time t3 is output as the phase data signal PFDS1. At time t4, the delayed clock signal FR2 rises to a high level. The value PFDCn + 1 of the count value PFDC at time t4 is output as the phase data signal PFDS2.

  In FIG. 11, at the rise of the feedback clock signal FD, at time t1, the value of the count value PFDC changes from PFDCn to PFDCn + 1. At this time t1, the reference clock signal FREF rises to a high level. Therefore, the value of the count value PFDC output as the phase data signal PFDS0 is a transition state value and is output as an indefinite value. At time t2, the delayed clock signal FR1 rises to a high level. The value PFDCn + 1 of the count value PFDC at time t2 is output as the phase data signal PFDS1. At time t3, the delayed clock signal FR2 rises to a high level. The value PFDCn + 1 of the count value PFDC at time t3 is output as the phase data signal PFDS2.

  Here, in the patterns of FIGS. 10 and 11, the values of the phase data signals PFDS0, PFDS1, and PFDS2 are PFDS0 ≠ PFDS1 = PFDS2.

  In FIG. 12, the value of the count value PFDC transits from PFDCn to PFDCn + 1 at time t1 when the feedback clock signal FD rises. At time t2, the reference clock signal FREF rises to a high level. The value PFDCn + 1 of the count value PFDC at time t2 is output as the phase data signal PFDS0. At time t3, the delayed clock signal FR1 rises to a high level. The value PFDCn + 1 of the count value PFDC at time t3 is output as the phase data signal PFDS1. At time t4, the delayed clock signal FR2 rises to a high level. The value PFDCn + 1 of the count value PFDC at time t4 is output as the phase data signal PFDS2. In this pattern, all values of the phase data signals PFDS0, PFDS1, and PFDS2 are PFDCn + 1 having the same value. Therefore, PFDS0 = PFDS1 = PFDS2.

  As described above, the seven patterns described above exist depending on the difference between the rising timing of the feedback clock signal FD and the rising timing of the reference clock signal FREF.

  The PFD selection circuit 107 outputs a selection phase data signal PFD_ONE according to the phase polarity signal PTDC_SIGN output from the TDC circuit 103, the phase difference detection signal PTDC, and the values of the phase data signals PFDS0, PFDS1, and PFDS2.

  The operation theory of the PFD selection circuit 107 will be described below. First, as described above, the phase difference detection signal PTDC output from the TDC circuit 103 indicates phase difference information within one cycle of the output clock FOUT between the reference clock signal FREF and the feedback clock signal FD that cannot be measured by the counters 101 and 102. Have. The phase difference detection signal PTDC includes a digital data value obtained by normalizing the phase difference between the reference clock signal FREF and the feedback clock signal FD within one cycle of the output clock FOUT, and the phase difference is ½ cycle of the output clock FOUT. A value indicating whether or not the above is stored in the MSB. In addition, the phase polarity signal PTDC_SIGN is a determination signal indicating the advance / delay of the phase of the feedback clock signal FD with respect to the reference clock signal FREF. For example, the phase polarity signal PTDC_SIGN is output as a low level, that is, a value of “0” when the feedback clock signal FD is delayed with respect to the reference clock signal FREF. When the feedback clock signal FD is advanced with respect to the reference clock signal FREF, a high level, that is, a value of “1” is output.

  For this reason, the PFD selection circuit 107 uses the phase polarity signal PTDC_SIGN output from the TDC circuit 103 and the phase difference detection signal PTDC to determine the phase relationship between the reference clock signal FREF and the feedback clock signal FD as shown in FIG. Can be determined.

  First, the pattern A is a case where the phase difference between the reference clock signal FREF and the feedback clock signal FD is less than ½ period of the output clock FOUT, and the phase of the reference clock signal FREF is ahead of the phase of the feedback clock signal FD. Show.

  Pattern B shows a case where the phase difference between the reference clock signal FREF and the feedback clock signal FD is ½ period or more of the output clock FOUT, and the phase of the reference clock signal FREF is delayed from the phase of the feedback clock signal FD. Yes.

  Pattern C shows a case where the phase difference between the reference clock signal FREF and the feedback clock signal FD is less than ½ period of the output clock FOUT, and the phase of the reference clock signal FREF is delayed from the phase of the feedback clock signal FD. Yes.

  Pattern D shows a case where the phase difference between the reference clock signal FREF and the feedback clock signal FD is greater than or equal to ½ period of the output clock FOUT, and the phase of the reference clock signal FREF is ahead of the phase of the feedback clock signal FD. Yes.

  Here, FIG. 14 shows a table summarizing the relationship between the patterns A to D shown in FIG. 13 and the MSBs of the phase polarity signal PTDC_SIGN and the phase difference detection signal PTDC. Thus, the phase relationship between the reference clock signal FREF and the feedback clock signal FD can be determined based on the MSB values of the phase polarity signal PTDC_SIGN and the phase difference detection signal PTDC.

  Here, the relationship between the phase data signals PFDS0, PFDS1, and PFDS2 shown in FIGS. 6 to 12 and the patterns A to D will be considered. First, it can be seen that the pattern of the reference clock signal FREF and the feedback clock signal FD shown in FIG. 6 corresponds to the pattern A or the pattern D from the delay relationship between the reference clock signal FREF and the delayed clock signals FR1 and FR2. Further, it can be seen that the patterns of the reference clock signal FREF and the feedback clock signal FD shown in FIG. 12 correspond to the pattern B or C. In both the patterns of FIGS. 6 and 12, the digital data values of the phase data signals PFDS0, PFDS1, and PFDS2 are the same value (PFDS0 = PFDS1 = PFDS2). That is, in the case of the pattern D or the pattern B, the phase difference between the reference clock signal FREF and the feedback clock signal FD is ½ period or more of the output clock FOUT. It can be assumed that a phase difference equal to or longer than the FD data transition time (tdFD) exists. Therefore, in this case, any value of the phase data signals PFDS0 to PFDS2 may be selected, and the PFD selection circuit 107 outputs the selected phase data signal as the selected phase data signal PFD_ONE.

  Next, in the patterns of the reference clock signal FREF and the feedback clock signal FD shown in FIGS. 7 and 8, the phase data signals PFDS0 and PFDS1 have the same value, but PFDS2 has a different value (PFDS0 = PFDS1 ≠ PFDS2). In this case, it is predicted that the rising edge of the feedback clock signal FD is in the vicinity of the rising edge of the reference clock signal FREF. Furthermore, it is predicted that the rising edge of the feedback clock signal FD is in the vicinity of the rising edges of the delayed clock signals FR1 and FR2.

  Here, it is assumed that the phase relationship between the reference clock signal FREF and the feedback clock signal FD is mostly in the pattern A state. Therefore, if the value of the phase polarity signal PTDC_SIGN is “0”, the PFD selection circuit 107 selects the phase data signal PFDS0 and outputs it as the selected phase data signal PFD_ONE. However, if it is difficult to satisfy the conditional expression 1 as described above, unlike the assumption, the TDC circuit 103 may output “1” as the value of the phase polarity signal PTDC_SIGN. In this case, it is assumed that the phase relationship between the reference clock signal FREF and the feedback clock signal FD is a pattern C state. Therefore, if the value of the phase polarity signal PTDC_SIGN is “1”, the PFD selection circuit 107 outputs digital data of a value (PFDS0 + 1) obtained by adding “1” to the value of the phase data signal PFDS0 as the selected phase data signal PFD_ONE. To do. As a result, accurate phase data matching the phase relationship measured by the TDC circuit 103 can be selected. In other states described below, data selection is performed using the state of the phase polarity signal PTDC_SIGN.

  Next, in the patterns of the reference clock signal FREF and the feedback clock signal FD shown in FIG. 9, the phase data signals PFDS0, PFDS1, and PFDS2 are all different values (PFDS0 ≠ PFDS1 ≠ PFDS2). In this case, it is predicted that the rising edge of the feedback clock signal FD is in the vicinity of the rising edge of the reference clock signal FREF. Here, it is assumed that the phase relationship between the reference clock signal FREF and the feedback clock signal FD is in the state of pattern A or pattern C. If the value of the phase polarity signal PTDC_SIGN is “0”, the PFD selection circuit 107 determines that it is the pattern A, selects the phase data signal PFDS0, and outputs it as the selected phase data signal PFD_ONE. Alternatively, if the value of the phase polarity signal PTDC_SIGN is “1”, the PFD selection circuit 107 determines that it is the pattern C, selects the phase data signal PFDS2, and outputs it as the selected phase data signal PFD_ONE.

  Next, in the patterns of the reference clock signal FREF and the feedback clock signal FD shown in FIGS. 10 and 11, the phase data signals PFDS1 and PFDS2 have the same value, but PFDS0 has a different value (PFDS0 ≠ PFDS1 = PFDS2). In this case, it is predicted that the rising edge of the feedback clock signal FD is in the vicinity of the rising edge of the reference clock signal FREF. Further, in this case, the relationship is opposite to that shown in FIGS. 7 and 8, and it is predicted that the rising edge of the feedback clock signal FD is ahead of the rising edge of the reference clock signal FREF.

  Here, it is assumed that the phase relationship between the reference clock signal FREF and the feedback clock signal FD is mostly in the pattern C state. Therefore, if the value of the phase polarity signal PTDC_SIGN is “1”, the PFD selection circuit 107 selects the phase data signal PFDS2 and outputs it as the selected phase data signal PFD_ONE. However, if the value of the phase polarity signal PTDC_SIGN is “0”, it is assumed that the phase relationship between the reference clock signal FREF and the feedback clock signal FD is in the pattern A state. Therefore, if the value of the phase polarity signal PTDC_SIGN is “0”, the PFD selection circuit 107 selects the digital data of the value (PFDS2-1) obtained by subtracting “1” from the value of the phase data signal PFDS2 as the selected phase data signal PFD_ONE. Output as.

  The above is the description of the operation theory of the PFD selection circuit 107. FIG. 15 shows a table summarizing the patterns of the selected phase data signal PFD_ONE that the PFD selection circuit 107 outputs by the above operation. As shown in FIG. 15, the PFD selection circuit 107 generates and outputs a selected phase data signal PFD_ONE according to the values of the phase data signals PFDS0, PFDS1, and PFDS2 and the value of the phase polarity signal PTDC_SIGN.

  The sampling circuit 108 captures each phase information at the clock timing of the output clock FOUT after the rising edge of the delayed clock signal FRn + 1, that is, after the data of each phase information is determined. Then, a signal having a digital value corresponding to the captured phase information is output to the phase error calculation circuit 109. The phase information referred to here is a phase difference detection signal PTDC, a count value signal PFRC, a selection phase data signal PFD_ONE, and a phase polarity signal PTDC_SIGN. The signals having digital values output from the sampling circuit 108 are PFR, PTD, DERR_PTDC_SIGN, and PFD. For convenience, the symbols “PFR”, “PTD”, “PFD”, and “DERR_PTDC_SIGN” indicate a digital signal name and a value stored in the digital signal. The digital signal PFR corresponds to the signal PFRC, the digital signal PTD corresponds to the phase difference detection signal PTDC, the digital signal DERR_PTDC_SIGN corresponds to the phase polarity signal PTDC_SIGN, and the digital signal PFD corresponds to the selected phase data signal PFD_ONE.

  FIG. 16 is a timing chart for explaining the operations of the PFD sample circuit 106 and the PFD selection circuit 107 which are characteristic parts of the ADPLL circuit 100. The same reference numerals in FIGS. 1 and 16 indicate the same signals. In this example, it is assumed that the phase of the reference clock signal FREF is delayed from the feedback clock signal FD and the rising edge of the feedback clock signal FD is in the vicinity of the rising edge of the reference clock signal FREF. That is, it corresponds to the pattern C in FIG.

  As shown in FIG. 16, the feedback clock signal FD rises at time t1. Corresponding to the rising edge of the feedback clock signal FD, the count value PFDC from the addition circuit 105 changes from “9” to “10” at time t2. At substantially the same time as time t2, the reference clock signal FREF also rises. In response to the rising edge of the reference clock signal FREF, the PFD sample circuit 106 takes in the count value PFDC. However, at time t2, the count value PFDC is in the middle of transition from “9” to “10”. For this reason, the count value PFDC taken in by the PFD sample circuit 106 becomes an indefinite value (“X” in the figure). This value is output from the PFD sample circuit 106 as the phase data signal PFDS0.

  Next, the delayed clock signal FR1 rises at time t3. In response to the rising edge of the delayed clock signal FR1, the PFD sample circuit 106 takes in the count value PFDC. The count value PFDC at this time has already transitioned, and the value is fixed to “10”. Therefore, the count value PFDC whose value is “10” is output from the PFD sample circuit 106 as the phase data signal PFDS1.

  Next, the delayed clock signal FR2 rises at time t4. In response to the rising edge of the delayed clock signal FR2, the PFD sample circuit 106 takes in the count value PFDC (value is “10”). The count value PFDC whose value is “10” is output from the PFD sample circuit 106 as the phase data signal PFDS2. Therefore, the values of the phase data signals PFDS0, PFDS1, and PFDS2 are PFDS0 ≠ PFDS1 = PFDS2.

  Here, the phase difference between the rising edges of the reference clock signal FREF and the feedback clock signal FD is approximately the period from time t1 to t2, and is equal to or less than ½ period of the output clock FOUT. Therefore, the MSB of the phase difference detection signal PTDC output from the TDC circuit 103 is “0”. Further, since the phase of the reference clock signal FREF is delayed from the feedback clock signal FD, the value of the phase polarity signal PTDC_SIGN output from the TDC circuit 103 is “1”. In addition, as described above, the values of the phase data signals PFDS0, PFDS1, and PFDS2 are PFDS0 ≠ PFDS1 = PFDS2. Therefore, as can be seen from FIG. 15, the PFD selection circuit 107 selects the value of the phase data signal PFDS2 and outputs it as the selected phase data signal PFD_ONE.

  When the sampling circuit 108 detects the rising edge of the delayed clock signal FRn + 1 output from the TDC circuit 103, the count value PFDC whose value is “10” and the value “10” at the clock timing of the output clock FOUT at time t5. The selected phase data signal PFD_ONE is captured.

  The phase error calculation circuit 109 receives the digital signals PFR, PTD, DERR_PTDC_SIGN, and PFD from the sampling circuit 108. The phase error calculation circuit 109 calculates (PFR− (PFD + PTD)) according to each value of the signal. Then, phase error data of the feedback clock signal FD with respect to the reference clock signal FREF is obtained according to the calculation result. The sign of PTD is determined by the value of DERR_PTDC_SIGN. By this calculation, the phase error calculation circuit 109 can derive a phase difference within one cycle of the output clock signal FOUT. The phase error calculation circuit 109 outputs the value of the phase error data as a digital data phase error signal PERR.

  The digital filter 110 filters the input phase error signal PERR in an arbitrary band, and outputs a control code DCON of the digital control oscillation circuit 111 according to the filtering data.

  A digitally controlled oscillation (DCO) circuit 111 (digitally controlled oscillator) generates and outputs an output clock signal FOUT at an oscillation frequency corresponding to the input control code DCON. The output clock output terminal 113 is a terminal that outputs the output clock signal FOUT from the DCO circuit 111 to an external circuit (not shown).

  Here, in the conventional ADPLL circuit 2, as shown in FIG. 23, the value of the digital data PFDC in the transition process at the rising timing of the reference clock signal FREF that is asynchronous with the feedback clock signal FD is converted into a phase error calculation circuit. 26 sometimes read. In this case, the phase error calculation circuit 26 calculates the phase error between the feedback clock signal FD and the reference clock signal FREF using the value of the indefinite digital data PFDC in the transition process. This phenomenon frequently occurs in the vicinity of the locked state in which the rising edges of the reference clock signal FREF and the feedback signal FD are about to synchronize. For this reason, the ADPLL circuit 2 cannot form a stable phase-locked loop.

  In the ADPLL circuit 100 of the present embodiment, the PFD sample circuit 106 uses the reference clock signal FREF that is asynchronous with the feedback clock signal FD and the delayed clock signals FR1 and FR2 obtained by sequentially delaying the reference clock signal FREF. The count value PFDC is taken in. Then, the PFD selection circuit 107 selects the most appropriate value from the three count values PFDC taken in by the PFD sample circuit 106. For the selection, data from the TDC circuit 103 is used. Then, an appropriate value selected by the PFD selection circuit 107 is used for the phase error calculation. As a result, it is possible to prevent indefinite digital data in the transition process from being used for the calculation of the phase error, and it is possible to form a stable phase locked loop by calculating the correct phase error data. .

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ADPLL circuit 101, 102 Counter 103 TDC circuit 104 Divider circuit 105 Adder circuit 106 PFD sample circuit 107 PFD selection circuit 108 Sampling circuit 109 Phase error calculation circuit 110 Digital filter 111 DCO circuit 112 Input terminal 113 Output terminal

Claims (8)

A first counter for counting a first clock signal;
A second counter for counting a second clock signal;
A delay clock generating circuit for generating first and second delayed clock signals obtained by sequentially delaying the first clock signal;
A sample circuit that samples the count value of the second counter with each of the first clock signal and the first and second delayed clock signals;
According to the phase difference between the first clock signal and the third clock signal obtained by dividing the second clock signal by a predetermined number, and the count value sampled by the first sample circuit, A selection circuit for selecting one of the count values sampled by the first sample circuit;
A phase error calculation circuit for calculating a phase difference between the first clock and the third clock according to the count value of the first counter and the count value selected by the selection circuit;
A digitally controlled oscillator that outputs the second clock according to a calculation result of the phase error calculation circuit;
A digital phase-locked loop circuit. The second counter is
A frequency dividing circuit for generating the third clock signal obtained by dividing the second clock signal by a predetermined number;
The digital phase-locked loop circuit according to claim 1, further comprising a third counter that counts the third clock signal. The digital phase-locked loop circuit according to claim 2, further comprising a phase difference detector that detects a phase difference between the first clock signal and the third clock signal within one cycle of the second clock signal. The phase detector is
A polarity value indicating a phase advance of the third clock signal with respect to the first clock signal;
4. The digital phase lock according to claim 3, wherein a determination value as to whether or not a phase difference between the first clock signal and the third clock signal is within a half cycle of the second clock signal is generated. Droop circuit. The selection circuit includes:
5. The count value sampled by the first sample circuit is selected according to the polarity value, the determination value, and the count value sampled by the first sample circuit. Digital phase locked loop circuit. The phase detector is
A first comparison result obtained by sequentially delaying the third clock signal and comparing the sequentially delayed clock signal with the first clock signal, and sequentially delaying the first clock signal and sequentially delaying the first clock signal. 4. A relative phase difference between the first clock signal and the third clock signal is detected according to a second comparison result obtained by comparing the clock signal with the third clock. 6. The digital phase locked loop circuit according to any one of 5 above. The phase detector includes the delay clock generation circuit,
7. The digital phase locked loop circuit according to claim 6, wherein the first and second delayed clock signals are used from a clock signal obtained by sequentially delaying the first clock signal by the phase detector. The amount of delay by which the phase detector sequentially delays the first clock signal is within a half period of the second clock signal, and more than a transition period in which the count value of the second counter transitions to the next value The digital phase-locked loop circuit according to claim 7.

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