KR101710450B1 - Phase locked loop and method for using the same - Google Patents

Abstract

A phase locked loop is disclosed. The phase locked loop of the present invention includes an introduction signal generating unit for generating an injection signal for each period of a reference clock signal; A voltage controlled oscillator for outputting a clock signal based on the introduction signal and an input control voltage; A first control loop for comparing the reference clock signal with an output signal of the voltage controlled oscillator to detect a first frequency difference and outputting a first control voltage of the voltage controlled oscillator based on the first frequency difference; And a rising edge of the voltage controlled oscillator output signal based on a rising edge and a falling edge of the reference clock signal and a first control voltage output from the first loop, And a second control loop for detecting a second frequency difference in a narrow range and outputting a second control voltage of the voltage controlled oscillator based on the second frequency difference.

Description

[0001] PHASE LOCKED LOOP AND METHOD FOR USING THE SAME [0002]

The present invention relates to a phase locked loop and a phase fixing method thereof, and more particularly, to an injection locked phase locked loop (ILPLL) based on a digital frequency locked loop and a method of fixing the phase locked loop.

A phase locked loop (PLL) produces a clock that synchronizes internal circuits in a system such as a transceiver. In particular, a Voltage Controlled Oscillator (VCO) or a Digitally Controlled Oscillator (DCO) is used to generate a clock of a specific frequency in a PLL (Phase Locked Loop) Will produce different frequencies depending on the semiconductor process, chip operating voltage, and temperature changes, so that they can be tailored to the desired frequency. That is, the frequency must be fixed. For this purpose, a frequency locked loop (FLL) is used, and a phase locked loop (PLL) is used to have a constant phase difference.

On the other hand, an injection fixed phase locked loop (ILPLL) is often used for fast frequency fixing because the frequency locking time determines the performance of the system. Although the injection-locked phase loop ILPLL has an advantage that the locking time can be made smaller than other phase locked loops (PLLs), the performance is determined by the performance of the frequency locked loop (FLL) There are disadvantages. In order to compensate for this, it is advantageous that the resolution of the frequency locked loop (FLL) can be made infinitely small when the analog method is applied. However, in this case, the control voltage for controlling the oscillator is kept constant A large capacitor is required. Also, when the frequency-locked loop (FLL) is implemented in a digital manner in order to reduce the area, the resolution is larger than that of the analog method, and the power consumption increases in order to reduce the resolution.

In addition, when the resolution of the frequency locked loop (FLL) used in the injection fixed phase locked loop (ILPLL) is large, the frequency of the clock generated in the oscillator is offset from the desired frequency. Since the injection locked phase locked loop (ILPLL) can not change the frequency of the oscillator and the output phase of the oscillator is adjusted to the reference clock for each period of the reference clock, the frequency offset is set to the injection fixed phase locked loop (ILPLL) Thereby increasing the long-term jitter of the signal. As such, increasing the long-term jitter increases the likelihood of data errors on the system. Therefore, a digital frequency detector capable of detecting fine frequency differences as much as possible is required. However, since the frequency detector for detecting the detailed frequency difference which has been proposed previously must have a high frequency band, the power consumption is increased.

Korean Registered Patent Registration No. 10-0937994 (Injection Locking Clock Generation Circuit and Clock Synchronization Circuit Using It, Hynix Semiconductor, 2010.01.21 Announcement)

Accordingly, the present invention seeks to provide a phase locked loop and a method of fixing the phase thereof, which improves system performance by detecting fine frequency differences without increasing the long-term jitter of the injection locked phase loop (ILPLL).
In addition, the present invention detects a frequency difference based on a difference between an edge of a reference clock and a rising edge of a feedback signal, thereby detecting a phase difference between the rising edge of the reference clock and the rising edge of the feedback signal, A fixed loop and a method of fixing the phase thereof.

According to an aspect of the present invention, there is provided a phase locked loop including: an injection signal generator for generating an injection signal for each period of a reference clock signal; A voltage controlled oscillator for outputting a clock signal based on the introduction signal and an input control voltage; And a control for detecting a frequency difference based on a rising edge and a falling edge of the reference clock signal and a rising edge of the voltage controlled oscillator output signal and outputting a control voltage of the voltage controlled oscillator based on the detected frequency difference, Loop.

Preferably, the control loop is the rising edge of the falling edge and the voltage controlled oscillator output signal of the rising edge and the voltage controlled oscillator outputs a rising difference value (diff ₁₎ and the reference clock signal of the edge of the signal of the reference clock signal the phase frequency detector to compare the difference value (diff ₂₎ for outputting an up signal (uP) or down signal (dOWN); And a voltage converting unit for outputting a control voltage corresponding to the up signal UP or the down signal DOWN.

Preferably, the phase frequency detector comprises: a time-to-digital converter (TDC) for converting the input time information to digital and then sampling it on the basis of the reference clock signal and outputting it to two output buses (THEM_POS, THEM_NEG); A code detector for comparing the output signals (THEM_POS, THEM_NEG) of the time-digital converter (TDC) to generate an up / down mode decision signal; And an up / down counter outputting an up / down signal based on the up / down mode decision signal generated in the code detector.

Preferably, the code detector samples the output signals (THEM_POS, THEM_NEG) of the time-digital converter (TDC) using a reference frequency and converts the sampled signals into an injection node and a long-term node Sampler; (Sh_Injection node, Sh_Long-term node) in which the least significant bit (LSB) starts with 1 by moving an injection node and a long-term node represented by 1 and 0, respectively, ; And determining whether the output frequency is faster or slower than the reference frequency by analyzing first and second signals (Sh_Injection node, Sh_Long-term node) output from the shifter, and based on the result, And a mode determining unit for determining the mode.

The control loop may further include a low pass filter (LPF) for removing noise included in the output signal of the voltage conversion unit.

According to another aspect of the present invention, there is provided a phase locked loop including: an introduction signal generating unit for generating an injection signal for each period of a reference clock signal; A voltage controlled oscillator for outputting a clock signal based on the introduction signal and an input control voltage; A first control loop for comparing the reference clock signal with an output signal of the voltage controlled oscillator to detect a first frequency difference and outputting a first control voltage of the voltage controlled oscillator based on the first frequency difference; And a rising edge of the voltage controlled oscillator output signal based on a rising edge and a falling edge of the reference clock signal and a first control voltage output from the first loop, And a second control loop for detecting a second frequency difference in a narrow range and outputting a second control voltage of the voltage controlled oscillator based on the second frequency difference.

Advantageously, the phase locked loop comprises: a first frequency divider for converting the frequency of the voltage controlled oscillator output signal to a lower frequency; And a second frequency divider that converts the frequency division ratio based on the converted frequency to maintain the initial frequency division ratio of the phase locked loop.

Preferably, the first control loop includes a first phase frequency detector that compares the reference clock signal with an output signal of the voltage controlled oscillator and outputs an up signal UP or a down signal DOWN; And a first voltage converting unit for outputting a first control voltage corresponding to the up signal UP or the down signal DOWN.

The first control loop may further include a first low pass filter (LPF) for removing noise included in the output signal of the first voltage converter.

Preferably, the falling edge and the voltage controlled oscillator output signal of the second control loop is the rising edge and the voltage controlled oscillator a difference value of the rising edge of the output signal (diff ₁₎ and the reference clock signal of the reference clock signal second phase and frequency detector for comparing the difference value (diff ₂₎ the rising edge outputs the up signal (uP) or down signal (dOWN); And a second voltage converting unit for outputting a second control voltage corresponding to the up signal UP or the down signal DOWN.

Preferably, the second phase frequency detector comprises: a time-to-digital converter (TDC) for converting the input time information to digital and then sampling it on the basis of the reference clock signal and outputting it to two output buses (THEM_POS, THEM_NEG); A code detector for comparing the output signals (THEM_POS, THEM_NEG) of the time-digital converter (TDC) to generate an up / down mode decision signal; And an up / down counter outputting an up / down signal based on the up / down mode decision signal generated in the code detector.

Preferably, the code detector samples the output signals (THEM_POS, THEM_NEG) of the time-digital converter (TDC) using a reference frequency and converts the sampled signals into an injection node and a long-term node Sampler; (Sh_Injection node, Sh_Long-term node) in which the least significant bit (LSB) starts with 1 by moving an injection node and a long-term node represented by 1 and 0, respectively, ; And determining whether the output frequency is faster or slower than the reference frequency by analyzing first and second signals (Sh_Injection node, Sh_Long-term node) output from the shifter, and based on the result, And a mode determining unit for determining the mode.

The second control loop may further include a second low pass filter (LPF) for removing noise included in the output signal of the second voltage converter.

According to another aspect of the present invention, there is provided a method of fixing a phase locked loop, comprising: comparing a reference clock signal of the phase locked loop with an output signal of the phase locked loop to detect a first frequency difference; step; Generating a first control voltage for controlling an output signal of the phase locked loop based on the first frequency difference; Deriving differences between the rising edge and the falling edge of the reference clock signal and the rising edge of the output signal of the phase locked loop output based on the first control voltage, respectively; Comparing the difference values to detect a second frequency difference; And generating a second control voltage for controlling the output signal of the phase locked loop based on the second frequency difference.

Preferably, the deriving step the difference value is further comprising: deriving a difference _{(diff. 1)} of the first rising edge of the rising edge of the first of said phase-locked loop output signal on the basis of the control voltage of the reference clock signal ; And deriving a difference value (diff ₂ ) between a polling edge of the reference clock signal and an N / 2 th (N divider) rising edge of the phase locked loop output signal output based on the first control voltage .

Advantageously, the first frequency difference detection step comprises the steps of: converting the frequency of the output signal of the phase locked loop to a lower frequency; And changing the frequency division ratio based on the converted frequency to maintain the initial frequency division ratio of the phase locked loop.

The present invention uses a time-to-digital converter (TDC) with a high resolution by detecting a frequency difference based on the difference between the edge of the reference clock and the rising edge of the feedback signal for frequency locking of the phase locked loop A detailed frequency difference is detected. In addition, the present invention detects fine frequency differences without increasing the long-term jitter of the injection locked phase loop (ILPLL). Thus, the present invention has the advantage of improving system performance.

1 is a schematic block diagram of a phase locked loop in accordance with an embodiment of the present invention.
2 is a timing chart for explaining the operation of the phase locked loop according to an embodiment of the present invention.
3 is a schematic block diagram of the offset frequency detector illustrated in FIG.
4 is a schematic block diagram of the code detector illustrated in FIG.
5 is a diagram for explaining a method for determining a mode of the up / down counter using the code detector illustrated in FIG.
6 is a flowchart illustrating a method of fixing a phase locked loop according to an exemplary embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Throughout the specification and claims, where a section includes a constituent, it does not exclude other elements unless specifically stated otherwise, but may include other elements.

1 is a schematic block diagram of a phase locked loop in accordance with an embodiment of the present invention. Referring to FIG. 1, a phase locked loop 100 according to an embodiment of the present invention includes an input signal generating unit (Inj.Con) 110, a first control loop 120, a second control loop 130, A control oscillator 140, a first frequency divider 150, and a second frequency divider 160.

The introduction signal generating unit (Inj.Con) 110 generates an introduction signal Inj_pulse for each period of the reference clock signal and outputs it to the voltage control oscillator 140.

The first control loop 120 generates a first control voltage in a direction that detects a rough frequency difference and reduces the difference based on the result. That is, the first control loop 120 compares the reference clock signal Ref _ck with the output signal OUT _ck of the voltage-controlled oscillator 140 to detect a rough frequency difference (e.g., a first frequency difference). And outputs a control voltage (e.g., a first control voltage) of the voltage-controlled oscillator 140 based on the frequency difference (e.g., the first frequency difference). To this end, the first control loop 120 includes a first phase frequency detector (FD) 121, a first digital converter 1 (DAC1) 122, a first low pass filter (Low) A pass filter (LPF) 123, and the like. The first phase frequency detector (FD) 121 compares the reference clock signal Ref _ck with the output signal OUT _ck of the voltage-controlled oscillator and outputs an up signal UP or a down signal DOWN. That is, when the output signal OUT _ck of the voltage-controlled oscillator is lower than the reference clock signal Ref _ck , it outputs the up signal UP, and in the opposite case, it outputs the down signal DOWN. The first voltage converter 122 outputs a first control voltage corresponding to the up signal UP or the down signal DOWN output from the first phase frequency detector (FD) 121. At this time, the first voltage conversion unit 122 converts the input digital signal into an analog signal and outputs the analog signal. A first low pass filter (LPF) 123 removes the noise included in the output signal of the first voltage converter 122.

The second control loop 130 is operated after adjusting the approximate frequency in the first control loop 120 and adjusts the frequency offset and generates a second control voltage based on the result. That is, the second control loop 130 outputs the difference between the rising edge and the falling edge of the reference clock signal _Refck and the rising edge of the output signal of the voltage-controlled oscillator 140, And detects a second frequency difference in a range narrower than the first frequency difference based on the first frequency difference. At this time, the output signal of the voltage controlled oscillator 140 is a signal that is output after being controlled based on the first control voltage output from the first loop 120. And outputs a second control voltage for controlling the output of the voltage controlled oscillator 140 based on the second frequency difference. To this end, the second control loop 130 includes a second phase frequency detector (Offset Frequency Detector, Offset FD) 131, a second voltage converter (Digital Analog Converter 2, DAC 2) 132, (LPF) 133. The low pass filter (LPF) The second phase frequency detector 131 receives a first difference value which is the difference between the rising edge of the reference clock signal _Refck and the rising edge of the output signal of the voltage controlled oscillator 140, (diff ₁₎ and up compared to the reference clock signal is a second difference value that is a difference between the falling edge (falling edge) and the voltage-controlled oscillator 140, the rising edge (rising edge) of the output signal (Ref _ck) (diff ₂₎ And outputs a signal UP or a down signal DOWN. That is, when the first difference value diff ₁ is greater than the second difference value diff ₂ , the output signal of the voltage controlled oscillator 140 is faster than the desired output signal, And outputs an up signal (UP) signal in the opposite case. The second voltage converter DAC2 132 outputs a second control voltage corresponding to the up signal UP or the down signal DOWN output from the second phase frequency detector (FD) 131. At this time, the second voltage converter 132 converts the input digital signal to analog and outputs the analog signal. The second low-pass filter (LPF) 133 removes the noise included in the output signal of the first voltage converter 132.

A voltage controlled oscillator (VCO) 140 outputs a clock signal OUT _ck based on an input signal Inj_pulse output from an input signal generating unit (Inj.Con) 110 and an input control voltage.

The first divider (Div1) 150 converts the frequency of the output signal of the voltage controlled oscillator (VCO) 140 to a low frequency. This is because the output signal of the voltage controlled oscillator (VCO) 140 may be too fast to operate the CMOS logic.

The second divider 160 divides the division ratio based on the frequency converted in the first divider Div1 to maintain the initial division ratio N of the phase locked loop 100. [

The present invention relates to a phase locked loop that fixes a frequency based on the difference between the edges of a reference clock signal and the edges of a feedback voltage controlled oscillator output signal, But is not limited to. For example, the phase locked loop of the present invention may be implemented to include only the second control loop 130 without including the first control loop 120. [

2 is a timing chart for explaining the operation of the phase locked loop according to an embodiment of the present invention. In general, if the oscillator output clock frequency is f _osc and the reference clock is f _ref , f _osc = N f _ref (N: division ratio) must be satisfied in the phase locked loop (PLL). When this condition is satisfied, the difference between the rising edge of the reference clock and the rising edge of the subsequent oscillator output clock, the falling edge of the reference clock, and the oscillator ) The difference between the rising edges of the output clocks is the same. Referring to FIG. 2, one cycle of the output signal OUT _ck of the voltage-controlled oscillator 140 of FIG. 1 is 1/8 of the reference clock Ref _ck . In other words, the voltage control oscillator 140 output signal OUT _ck is obtained by dividing the reference clock Ref _ck by the division ratio of 8. The difference t _ref between the rising edge of the reference clock and the rising edge of the output signal OUT _ck of the subsequent oscillator 140 is proportional to the falling edge of the reference clock, the difference (t _os) of the rising edge of the signal (OUT _ck), indicates that, as in the example of Figure 2, equal to the voltage-controlled oscillator (140) output signal (OUT _ck), matches the desired frequency, if the voltage-controlled oscillator ( T _ref > t _os when the output signal OUT _ck is slower than the desired frequency, and t _ref > t _os when the output signal OUT _{ck of the} voltage controlled oscillator 140 is faster than the desired frequency.

FIG. 3 is a schematic block diagram of an offset frequency detector (also referred to as a second phase frequency detector) 131 illustrated in FIG. Referring to FIG. 3, the second phase frequency detector 131 includes a time-to-digital converter (TDC) 210, a code detector 220, and an up / down counter 230.

A time-to-digital converter (TDC) 210 converts the input time information into a digital signal, samples it based on a reference clock signal, and outputs it to the two output buses THEM_POS and THEM_NEG.

The code detector 220 compares the output signals (THEM_POS, THEM_NEG) of the time-to-digital converter (TDC) 210 to generate an up / down mode decision signal.

The up / down counter 230 outputs an up / down signal based on the up / down mode decision signal generated by the code detector 220.

4 is a schematic block diagram of the code detector 220 illustrated in FIG. Referring to FIG. 4, the code detector 220 includes a sampler 221, a shifter 222, and a mode determination unit 223.

The sampler 221 samples the output signals THEM_POS and THEM_NEG of the time-digital converter (TDC) using the reference frequency and converts the sampling signals into an injection node and a long-term node. Referring to FIG. 5A, the injection node is '0001111100000000', the long-term node is '0001111111000000', and the injection node (Injection) node is '0001111100000000', and the long-term node is '0001111100000000'.

The shifter 222 shifts the injection node and the long-term node represented by '1' and '0', respectively, as in the example of FIG. 5 to shift the least significant bit (LSB) 1 '(Sh_Injection node, Sh_Long-term node). Referring to FIGS. 5 (a) and 5 (b), all three bits are shifted leftward.

The mode determining unit 223 analyzes the first and second signals (Sh_Injection node, Sh_Long-term node) output from the shifter 222 to determine whether the output frequency is faster or slower than the reference frequency, Determines the mode of the up / down counter. To this end, the mode determination unit 223 detects a bit whose bit value of the first signal (Sh_Injection node) output from the shifter 222 changes from '1' to '0' and stores the bit in the En_Injection node And detects a bit whose bit value of a second signal (Sh_Long-term node) output from the shifter changes from '1' to '0', and stores the detected bit in a second bus (En_Long-term node_Eq). On the other hand, the En_Long-term node changes the bit of the second signal (Sh_Long-term node) from '1' to '0' and all subsequent bits to '1'. Finally, the mode bus stores a result of ANDing the bit values of the first bus (En_Injection node) and the third bus (En_Long-term node) on a bit-by-bit basis. At this time, when all the bit values of the mode bus are 0, it means that the output frequency of the voltage controlled oscillator (140 in FIG. 1) is slow. Therefore, the mode is determined in the direction of increasing the output of the up / down counter (230 in FIG. 3). On the other hand, if all the bit values of the mode bus are not 0 but 1, the output frequency of the voltage controlled oscillator (140 in FIG. 1) is fast. Therefore, the mode is determined in the direction of reducing the output of the up / down counter (230 in FIG. 3).

5 is a diagram for explaining a method for determining a mode of the up / down counter using the code detector illustrated in FIG. FIG. 5A shows a case where the output frequency of the oscillator is slow because all the bit values of the last mode bus are '0', FIG. 5B shows a case where the bit values of the last mode bus (7th bit value) is '1', it indicates that the output frequency of the oscillator is fast.

6 is a flowchart illustrating a method of fixing a phase locked loop according to an exemplary embodiment of the present invention. Referring to FIGS. 1 and 6, a phase locking method of a phase locked loop according to an embodiment of the present invention is as follows.

First, in step S110, a first phase frequency detector (FD) 121 detects a rough first frequency difference. That is, a rough frequency difference (e.g., a first frequency difference) is detected by comparing the reference clock signal Ref _ck of the phase locked loop 100 with the output signal OUT _ck of the phase locked loop 100. At this time, if the frequency of the output signal of the phase locked loop 100 is too high, the phase of the phase locked loop 100 output signal may be too fast to operate the CMOS logic, (Not shown) of changing the frequency division ratio based on the converted frequency to maintain the initial frequency division ratio N of the phase locked loop 100. [

In step S120, the first voltage conversion unit (DAC1) 122 generates and outputs a control voltage (e.g., a first control voltage) of the voltage-controlled oscillator 140 based on the first frequency difference.

In step S130, the second phase frequency detector (Offset FD) 131 detects the rising edge and falling edge of the reference clock signal _Refck and the rising edge of the output signal of the voltage controlled oscillator 140, Compare the rising edge. At this time, the output signal of the voltage controlled oscillator 140 is a signal that is output after being controlled based on the first control voltage output from the first loop 120.

In step S140, the second phase frequency detector (Offset FD) 131 detects the difference between the rising edge of the reference clock signal _Refck and the rising edge of the output signal of the voltage-controlled oscillator 140 And derives the first difference value diff ₁ .

In step S150, the difference between the second phase frequency detector (Offset FD) (131) the reference clock signal (Ref _ck) falling edge (falling edge) and the voltage-controlled oscillator 140, the rising edge (rising edge) of the output signal of the And derives a second difference value (diff ₂ ).

In step S160, a second phase frequency detector (Offset FD) 131 compares the first difference value diff ₁ and the second difference value diff ₂ .

In step S170, the second phase frequency detector (Offset FD) 131 detects the second frequency difference based on the comparison result of step S160.

In step S180, the second voltage converter DAC2 (132) rk generates and outputs a control voltage (e.g., a second voltage) of the voltage-controlled oscillator 140 based on the second frequency difference.

The above-described embodiments of the present invention can be embodied in a general-purpose digital computer that can be embodied as a program that can be executed by a computer and operates the program using a computer-readable recording medium.

The computer readable recording medium includes a magnetic storage medium (e.g., ROM, floppy disk, hard disk, etc.), optical reading medium (e.g., CD ROM, DVD, etc.).

The present invention has been described with reference to the preferred embodiments.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (16)

In the phase locked loop,
An introducing signal generator for generating an injection signal for each period of the reference clock signal;
A voltage controlled oscillator for outputting a clock signal based on the introduction signal and an input control voltage; And
A control loop for detecting a frequency difference based on a difference between a rising edge and a falling edge of the reference clock signal and a rising edge of the voltage controlled oscillator output signal and outputting a control voltage of the voltage controlled oscillator based on the frequency difference, , ≪ / RTI &
The control loop
A difference value (diff ₂₎ the rising edge of the falling edge and the voltage controlled oscillator output signal of the reference clock rising edge and said voltage controlled oscillator outputs a rising difference value (diff ₁₎ and the reference clock signal edge of the signal of the signal A phase frequency detector for comparing the up signal UP or the down signal DOWN; And
And a voltage converter for outputting a control voltage corresponding to the up signal UP or the down signal DOWN.
delete The apparatus of claim 1, wherein the phase frequency detector
A time-to-digital converter (TDC) for converting the input time information into a digital signal, sampling it based on the reference clock signal, and outputting it to two output buses (THEM_POS, THEM_NEG);
A code detector for comparing the output signals (THEM_POS, THEM_NEG) of the time-digital converter (TDC) to generate an up / down mode decision signal; And
And an up / down counter outputting an up / down signal based on the up / down mode decision signal generated by the code detector.
4. The apparatus of claim 3, wherein the code detector
A sampler for sampling the output signals (THEM_POS, THEM_NEG) of the time-digital converter (TDC) using a reference frequency and converting the sampling signals into an injection node and a long-term node;
(Sh_Injection node, Sh_Long-term node) in which the least significant bit (LSB) starts with 1 by moving an injection node and a long-term node represented by 1 and 0, respectively, ; And
(Sh_Injection node, Sh_Long-term node) output from the shifter, determines whether the output frequency is faster or slower than the reference frequency, and determines a mode of the up / down counter based on the result And a mode determining unit for determining a phase of the phase locked loop.
2. The apparatus of claim 1, wherein the control loop
And a low-pass filter (LPF) for removing noise included in an output signal of the voltage converter.
In the phase locked loop,
An introducing signal generator for generating an injection signal for each period of the reference clock signal;
A voltage controlled oscillator for outputting a clock signal based on the introduction signal and an input control voltage;
A first control loop for comparing the reference clock signal with an output signal of the voltage controlled oscillator to detect a first frequency difference and outputting a first control voltage of the voltage controlled oscillator based on the first frequency difference; And
Based on a difference between a rising edge and a falling edge of the reference clock signal and a rising edge of the voltage controlled oscillator output signal output based on the first control voltage output from the first control loop, And a second control loop for detecting a second frequency difference in a narrow range and outputting a second control voltage of the voltage controlled oscillator based on the second frequency difference,
The second control loop
A difference value (diff ₂₎ the rising edge of the falling edge and the voltage controlled oscillator output signal of the reference clock rising edge and said voltage controlled oscillator outputs a rising difference value (diff ₁₎ and the reference clock signal edge of the signal of the signal A second phase frequency detector for outputting an up signal UP or a down signal DOWN by comparison; And
And a second voltage converter for outputting a second control voltage corresponding to the up signal UP or the down signal DOWN.
7. The method of claim 6, wherein the phase locked loop
A first frequency divider for converting the frequency of the voltage controlled oscillator output signal to a low frequency; And
Further comprising a second divider to convert the frequency division ratio based on the converted frequency to maintain an initial frequency division ratio of the phase locked loop.
7. The method of claim 6, wherein the first control loop
A first phase frequency detector for comparing the reference clock signal with an output signal of the voltage controlled oscillator and outputting an up signal UP or a down signal DOWN; And
And a first voltage converter for outputting a first control voltage corresponding to the up signal UP or the down signal DOWN.
9. The method of claim 8, wherein the first control loop
And a first low pass filter (LPF) for removing noise included in the output signal of the first voltage converter.
delete 7. The apparatus of claim 6, wherein the second phase frequency detector
A time-to-digital converter (TDC) for converting the input time information into a digital signal, sampling it based on the reference clock signal, and outputting it to two output buses (THEM_POS, THEM_NEG);
A code detector for comparing the output signals (THEM_POS, THEM_NEG) of the time-digital converter (TDC) to generate an up / down mode decision signal; And
And an up / down counter outputting an up / down signal based on the up / down mode decision signal generated by the code detector.
12. The apparatus of claim 11, wherein the code detector
A sampler for sampling the output signals (THEM_POS, THEM_NEG) of the time-digital converter (TDC) using a reference frequency and converting the sampling signals into an injection node and a long-term node;
(Sh_Injection node, Sh_Long-term node) in which the least significant bit (LSB) starts with 1 by moving an injection node and a long-term node represented by 1 and 0, respectively, ; And
(Sh_Injection node, Sh_Long-term node) output from the shifter, determines whether the output frequency is faster or slower than the reference frequency, and determines a mode of the up / down counter based on the result And a mode determining unit for determining a phase of the phase locked loop.
7. The method of claim 6, wherein the second control loop
And a second low-pass filter (LPF) for removing noise included in an output signal of the second voltage converter.
In a phase locking method of a phase locked loop,
Comparing a reference clock signal of the phase locked loop with an output signal of the phase locked loop to detect a first frequency difference;
Generating a first control voltage for controlling an output signal of the phase locked loop based on the first frequency difference;
Deriving differences between the rising edge and the falling edge of the reference clock signal and the rising edge of the output signal of the phase locked loop output based on the first control voltage, respectively;
Comparing the difference values to detect a second frequency difference; And
Generating a second control voltage for controlling an output signal of the phase locked loop based on the second frequency difference,
The difference value derivation step
Deriving the difference _{(diff. 1)} of the first rising edge of the reference clock and the rising edge of the first of said phase-locked loop output signal on the basis of a control voltage signal; And
Deriving a difference value (diff ₂ ) between a polling edge of the reference clock signal and an N / 2th (N is the division ratio) rising edge of the phase locked loop output signal output based on the first control voltage The phase of the phase-locked loop is set to a predetermined value.
delete 15. The method of claim 14, wherein the first frequency difference detection step
Converting the frequency of the output signal of the phase locked loop to a lower frequency; And
Further comprising changing the frequency division ratio based on the converted frequency to maintain an initial frequency division ratio of the phase locked loop.

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