KR20090033783A - All digital phase locked loop controlling by digital code and method controlling the same - Google Patents

Abstract

A digital phase locked loop circuit and a control method thereof are provided to reduce a phase tracking time by setting the relation between a reference clock signal and the phase when the digital phase looked loop circuit is on. A digital phase frequency detector detects the phase difference and the frequency difference by comparing a reference clock signal with an output signal of the digital phase looked loop circuit. The digital phase frequency detector outputs the detected phase difference and the frequency difference as the digital format. A digital loop filter(120) receives an output signal of the digital phase frequency detector and outputs the control voltage signal of the digital format. A digital control oscillator(130) receives the control voltage signal and outputs the received signal to the output terminal of the digital phase locked loop circuit and the digital phase frequency detector. The controller(150) determines whether the reference clock signal is applied to the digital control oscillator in response to the on/off signal corresponding to the on or off state of the digital phase locked loop circuit and the reference clock signal.

Description

Digital phase locked loop controlling by digital code and controlling method thereof {All digital phase locked loop controlling by digital code and method controlling the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly, to an all digital phase locked loop circuit controlled by a digital code and a control method thereof.

Generally, PLL (Phase Locked Loop) is mainly used in communication system or video signal reproduction, and it is fixed by detecting and adjusting the phase and frequency change of output signal which may be generated by external environment. Generates an output signal having a predetermined phase and frequency.

An example of a phase locked loop controlled by a digital code is a digital phase locked loop circuit (ADPLL: All Digital PLL). The digital phase locked loop circuit ADPLL may include a digital phase frequency detector, a digital loop filter, a digital controlled oscillator, and a divider. The operation of each component of the digital phase locked loop circuit ADPLL is similar to the digital phase locked loop circuit PLL. That is, the digital phase frequency detector compares a reference clock signal and an output signal of the divider, compares phase and frequency, and generates an error value corresponding to a phase difference and a frequency difference between the two clocks. The digital loop filter digitally controls a control voltage signal for controlling an output signal of the digital phase frequency detector when an error value generated by the digital phase frequency detector is larger than a reference error value allowed by the digital phase locked loop circuit. Output to the oscillator. The digitally controlled oscillator controls and outputs a phase and a frequency of the output signal in response to the control voltage signal. The divider divides the output signal into a predetermined division value and outputs the divided signal to the digital phase frequency detector so that the phase and frequency of the reference clock signal and the output signal are repeatedly compared.

The signal output from the digital loop filter of the digital phase locked loop circuit ADPLL has a digital value. That is, the control voltage signal applied to the digitally controlled oscillator has a digital value. As described above, when the digital phase-locked loop circuit controlled by the digital code repeats the off state and the on state, the control voltage of the digitally controlled oscillator is stored when it is changed from the off state to the on state. There is no need for a frequency locking operation. However, since the relationship between the reference clock signal and the phase is unknown, conventionally, the phase tracking for resetting the relationship between the reference clock signal and the phase when the digital phase locked loop circuit PLL is changed from an off state to an on state ( tracking time was required.

An object of the present invention is to reduce phase tracking time when the digital phase locked loop circuit is changed from an off state to an on state in a digital phase locked loop circuit controlled by a digital code. To provide a digital phase locked loop circuit.

Another object of the present invention is to provide a method of controlling the digital phase locked loop circuit.

According to an embodiment of the present invention, an all-phase phase locked loop circuit compares a reference clock signal and an output signal of the digital phase-locked loop circuit to detect a phase difference and a frequency difference, A digital phase frequency detector for outputting the form, a digital loop filter for receiving an output signal of the digital phase frequency detector and outputting a control voltage signal in digital form, an output terminal of the digital phase locked loop circuit for receiving the control voltage signal, and A digitally controlled oscillator for outputting to a digital phase frequency detector and an on / off signal corresponding to an on state or an off state of the digital phase locked loop circuit and the digital controlled oscillator in response to the reference clock signal. Control unit for determining whether to apply the reference clock signal It may be provided.

Preferably, the controller applies the reference clock signal to the digitally controlled oscillator in response to the on / off signal corresponding to the on state of the digital phase locked loop circuit.

The controller controls the reference clock signal to be input to the digitally controlled oscillator after the on / off signal corresponding to the on state of the digital phase locked loop circuit is applied and a predetermined time for frequency locking has elapsed. desirable.

The controller may be configured to control the reference clock signal to be input to the digitally controlled oscillator after the on / off signal corresponding to the on state of the digital phase locked loop circuit is applied and the reference clock signal has passed one clock. Do.

Preferably, the controller applies only one clock signal to the digital control oscillator in response to the on / off signal corresponding to the on state of the digital phase locked loop circuit.

Preferably, the digital phase locked loop circuit further includes a bandwidth controller for controlling a bandwidth of an output signal of the digital phase frequency detector.

The bandwidth controller preferably extends the bandwidth of the output signal of the digital phase frequency detector and decreases the bandwidth whenever the output signal of the digital phase locked loop circuit intersects with the reference clock signal.

Preferably, the bandwidth controller controls the digital loop filter to control a bandwidth of an output signal of the digital phase locked loop circuit.

Preferably, the digital phase locked loop circuit further includes a divider for dividing the output signal and outputting the divided signal to the digital phase frequency detector.

The digital phase locked loop circuit may further include a delay unit configured to delay the reference clock signal by the delay amount of the output signal by the divider and output the delayed reference clock signal to the digital phase frequency detector.

The digital phase locked loop circuit may further include a DA converter converting the digital control voltage signal into an analog form and outputting the analog voltage to the digital controlled oscillator.

According to another aspect of the present invention, there is provided a method for controlling an all-phase phase locked loop circuit, the method for controlling a digital phase locked loop circuit having a digitally controlled oscillator. Determining whether the digital phase locked loop circuit is in an on state or an off state and applying a reference clock signal to the digital controlled oscillator when the digital phase locked loop circuit is changed from an off state to an on state. .

The applying of the reference clock signal may include applying the reference clock signal to the digitally controlled oscillator after the digital phase locked loop circuit is changed from an off state to an on state and a predetermined time for frequency locking has elapsed. It is desirable to.

The control method of the digital phase locked loop circuit may include comparing the reference clock signal and an output signal of the digital phase locked loop circuit, detecting a phase difference and a frequency difference, and outputting a digital phase frequency detection signal and the phase frequency. Preferably, the method further includes controlling a bandwidth of the detection signal.

The controlling of the bandwidth preferably includes extending the bandwidth of the phase frequency detection signal and decreasing the bandwidth whenever the output signal of the digital phase locked loop circuit and the reference clock signal cross each other. .

A digital phase locked loop circuit and a control method thereof controlled by a digital code according to the present invention provide a quick relationship between the reference clock signal and a phase when the digital phase locked loop circuit is changed from an off state to an on state. Since it can be set again, there is an advantage that the phase tracking time can be reduced.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram of a digital phase locked loop (PLL) 100 according to an embodiment of the present invention.

Referring to FIG. 1, a digital phase locked loop (PLL) 100 may include a digital phase frequency detector 110, a digital loop filter 120, and a digital controlled oscillator. Oscillator 130 and the controller 150 may be provided. In addition, the digital phase locked loop (PLL) 100 may further include a divider 140, a delay unit 160, and a bandwidth controller 170.

The digital phase frequency detector 110 detects a phase difference and a frequency difference by comparing the reference clock signal CLK_ref and the output signal CLK_vco of the digital phase locked loop circuit ADPLL 100. When the digital phase locked loop circuit 100 further includes a divider 140, the digital phase frequency detector 110 compares the reference clock signal CLK_ref with the output signal CLK_div of the divider 140. The phase difference and frequency difference are detected and a phase frequency detection signal in a digital form is output. The digital phase frequency detector 110 may be implemented as a Bang-Bang Phase Frequency Detector. The bang bang digital phase frequency detector is a kind of digital phase frequency detector which detects the phase difference and the frequency difference and outputs it as a binary code. The structure of the bang bang digital phase frequency detector has a general knowledge in the art. As it is known to grow, detailed description of the structure is omitted.

The digital loop filter 120 outputs a control voltage signal in digital form in response to the phase frequency detection signal. That is, when the error value corresponding to the phase difference and the frequency difference between the two signals output from the digital phase frequency detector 110 is larger than the reference error value allowed by the digital phase lock loop circuit 100, the digital phase frequency detector A digital control voltage signal Vctrl for controlling the output signal of 110 is output to the digital controlled oscillator 130.

The digitally controlled oscillator 130 controls and outputs the phase and frequency of the output signal CLK_vco in response to the control voltage signal Vctrl. The divider 140 divides the output signal into a predetermined division value and outputs the output signal to the digital phase frequency detector 110 so that the phase and frequency of the reference clock signal CLK_ref and the output signal CLK_div are repeatedly compared.

The delay unit 160 delays the reference clock signal CLK_ref as much as the output signal CLK_vco of the digitally controlled oscillator 130 is delayed while passing through the divider 140. That is, the delay unit 160 delays the reference clock signal CLK_ref as much as the output signal CLK_div of the divider 140 is delayed compared to the output signal CLK_vco of the digitally controlled oscillator 130.

Although not shown in FIG. 1, the digital phase locked loop circuit 100 may further include a DA to D converter. Since the control voltage signal Vctrl is a digital signal, the DA converter converts the control voltage signal Vctrl into an analog form and applies it to the digital control oscillator 130. It will be apparent to those skilled in the art that the DA converter may be provided between the digital loop filter 120 and the digitally controlled oscillator 130 or may be included inside the digitally controlled oscillator 130. It is.

The controller 150 controls the digitally controlled oscillator 130, the digital loop filter 120, and the divider 140 in response to the on / off signal ON / OFF and the reference clock signal CLK_ref. That is, the controller 150 controls the digitally controlled oscillator in response to the on / off signal (ON / OFF) when the digital phase locked loop circuit (PLL) 100 is changed from an off state to an on state. The reference clock signal INJECTION is applied to 130. Hereinafter, the reference clock signal INJECTION output from the controller 150 to the digitally controlled oscillator 130 is displayed differently from the reference clock signal CLK_ref applied to the controller 150. That is, the reference clock signal INJECTION is a signal that is output to the digitally controlled oscillator 130 through the control unit 150 by modifying or modifying the reference clock signal CLK_ref for only a predetermined time. The reference clock signal INJECTION is essentially a signal derived from the reference clock signal CLK_ref even though the waveform is different from the reference clock signal CLK_ref. Detailed operations of the controller 150 will be described in detail with reference to FIG. 4.

The bandwidth controller 170 controls the output signal of the digital phase frequency detector 110, that is, the bandwidth of the phase frequency detection signal. The bandwidth controller 170 expands the bandwidth of the phase frequency detection signal, and then the output signal of the digital phase locked loop circuit 100, that is, the output signal CLK_div of the divider 140 is a reference clock signal CLK_ref. Every time it crosses with, the bandwidth is reduced. Specific operations of the bandwidth controller 170 will also be described in detail with reference to FIG. 4.

FIG. 2 is a diagram illustrating an internal circuit of the digitally controlled oscillator 130 of FIG. 1.

1 and 2, the digitally controlled oscillator 130 may be represented by a plurality of inverters connected in series. When the digital phase locked loop circuit 100 is changed from an off state to an on state, the controller 150 applies a reference clock signal INJECTION to an output terminal of the digitally controlled oscillator 130. The reference clock signal INJECTION may be applied to the output terminal of the digitally controlled oscillator 130 through a predetermined buffer.

3 is a block diagram illustrating an embodiment of the digital loop filter 120 of FIG. 1.

1 and 3, the digital loop filter 120 may include a sub digital loop filter 330, a comparator 340, and a counter 350. That is, by adding the comparator 340 and the counter 350 to a general digital phase locked loop circuit, the digital control voltage signal Vctrl may be output. In FIG. 3, the DA converter 310 that is not shown in FIG. 1 is illustrated. As described above, the DA converter 310 may be provided between the digital loop filter 120 and the digitally controlled oscillator 130 as shown in FIG. 3 or may be provided inside the digitally controlled oscillator 130.

The sub digital loop filter 330 performs the same function as the digital loop filter of the digital phase locked loop circuit. The comparator 340 compares the output signal of the sub digital loop filter 330 with the output signal of the DA converter 310, and the counter 350 counts the output signal of the comparator 340 so that the control voltage signal Vctrl is It has a digital form.

In FIG. 3, the embodiment of the digital loop filter 120 having the comparator 340 and the counter 350 has been described. However, if the control voltage signal Vctrl can be converted into a digital form even when the configuration is different, It is apparent to those skilled in the art that the same effects as the present invention can be obtained.

4 is a waveform diagram of signals used in the operation of the digital phase locked loop circuit 100 of FIG.

5 is a flowchart of a control method of the digital phase locked loop circuit 100 of FIG. 1.

1, 4 and 5, first, it is determined whether the digital phase locked loop circuit 100 is on or off (step S510). The digital phase locked loop circuit 100 is turned off until t1 time and then turned on at time t1. That is, when the on / off signal (ON / OFF) is in the first logic state, the digital phase locked loop circuit 100 is in the off state and the digital phase lock loop when the on / off signal (ON / OFF) is in the second logic state. The circuit 100 is on. Hereinafter, the first logic state means a logic high state and the second logic state means a logic low state. However, it is apparent to those skilled in the art that the same effect as the present invention can be obtained even when the first logic state and the second logic state have opposite logic states.

When the digital phase locked loop circuit 100 is changed from an off state to an on state, the digital control oscillator 130 performs frequency locking by using a control voltage value which is already stored from time t1 to time t2. Although FIG. 4 illustrates a case in which frequency locking is performed from a time t1 to a time t2 corresponding to one clock of the reference clock signal CLK_ref, the same effect as the present invention can be obtained even if the frequency locking is performed for a longer time. It is obvious to those skilled in the art. After the time for frequency locking has elapsed, the controller 150 applies a reference clock signal INJECTION to the digitally controlled oscillator 130 (step S520). 4 illustrates a case in which the control unit 150 applies the reference clock signal INJECTION to the digitally controlled oscillator 130 at time t3 after the time t2 has elapsed. FIG. 4 illustrates a case where the reference clock signal INJECTION is in opposite logic state and the same phase as the reference clock signal CLK_ref. That is, the reference clock signal INJECTION is in a second logic state between time t2 and time t3 and in a first logic state between time t3 and t4. However, the above case is only an example, and the same effects as those of the present invention can be obtained even when the reference clock signal INJECTION has the same logic state and the same phase as the reference clock signal CLK_ref. It is obvious to those skilled in the art.

In addition, in FIG. 4, only one clock is applied to the reference clock signal INJECTION to set the phase relationship with the reference clock signal CLK_ref. However, even when the reference clock signal INJECTION is two or more clocks, the same effect as in the present invention is achieved. It is obvious to those skilled in the art that it can be obtained.

After the reference clock signal INJECTION is applied, that is, at time t4, the hold signal HOLD and the reset signal RESET are changed from the first logic state to the second logic state. The hold signal HOLD turns off the digital loop filter 120 in the first logic state and turns on the digital loop filter 120 in the second logic state. The reset signal RESET turns off the divider 160 in the first logic state and turns on the divider 140 in the second logic state. Accordingly, the digital loop filter 120 and the divider 160 remain in the off state, but after the time t4 when the reference clock signal INJECTION is applied to the digital controlled oscillator 130, the digital loop filter 120 and the divider 160 160 is changed to the on state. That is, after the time t4, the digital loop filter 120 outputs the digital control voltage signal Vctrl and the divider 140 outputs the output signal CLK_div to the digital phase frequency detector 110. At the time t4, the phase relationship between the output signal CLK_div of the divider 140 and the reference clock signal CLK_ref is set.

However, in this case, the output signal CLK_div of the divider 140 and the reference clock signal CLK_ref may not be matched with each other and may shift. Accordingly, the bandwidth controller 170 expands the bandwidth of the phase frequency detection signal, which is an output signal of the digital phase frequency detector 110 (step S530). That is, at time t5, the phase frequency detection signal is changed from the second logic state to the first logic state. In the case where the bandwidth of the phase frequency detection signal is expanded four times at time t5, the output signal CLK_div and the reference clock signal CLK_ref of the frequency divider 140 do not cross after the time t5 and before the time t6. However, at time t6, since the output signal CLK_div and the reference clock signal CLK_ref of the divider 140 cross each other, the bandwidth of the phase frequency detection signal is reduced at time t6 (S540). In the case where the bandwidth of the phase frequency detection signal is reduced from 4 times to 2 times at time t6, the output signal CLK_div and the reference clock signal CLK_ref of the divider 140 cross over from time t6 to time t7. I never do that. However, at time t7, since the output signal CLK_div and the reference clock signal CLK_ref of the divider 140 cross each other, the bandwidth of the phase frequency detection signal is decreased again at time t7 (S540). In the case where the bandwidth of the phase frequency detection signal is reduced from 2 times to 1 times at time t6, the phases of the output signal CLK_div and the reference clock signal CLK_ref of the divider 140 are continuously matched. It can be seen that. As described above, the bandwidth of the phase frequency detection signal is extended, and then, whenever the output signal CLK_div and the reference clock signal CLK_ref of the divider 140 cross each other, the bandwidth of the phase frequency detection signal is decreased. The phase of the output signal CLK_div and the reference clock signal CLK_ref of the period 140 may be matched.

In FIG. 4, the bandwidth of the phase frequency detection signal is reduced from 4 times to 2 times and 1 times. However, when the bandwidth of the phase frequency detection signal is expanded or reduced to another size (for example, the bandwidth of the phase frequency detection signal is reduced. It is obvious to the person skilled in the art that the same effect as the present invention can be obtained even when expanding to 8 times and then reducing to 4 times, 2 times, 1).

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of an all digital phase locked loop circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an internal circuit of the digitally controlled oscillator of FIG. 1.

3 is a block diagram illustrating an embodiment of the digital loop filter of FIG. 1.

4 is a waveform diagram of signals of the digital phase locked loop circuit of FIG.

5 is a flowchart of a control method of the digital phase locked loop circuit of FIG. 1.

Claims (21)

In a digital phase locked loop circuit controlled by a digital code, A digital phase frequency detector configured to compare a reference clock signal and an output signal of the digital phase locked loop circuit to detect a phase difference and a frequency difference and output the digital phase frequency detector; A digital loop filter receiving the output signal of the digital phase frequency detector and outputting a digital control voltage signal; A digital controlled oscillator receiving the control voltage signal and outputting the control voltage signal to an output terminal of the digital phase locked loop circuit and the digital phase frequency detector; And A controller configured to determine whether to apply the reference clock signal to the digitally controlled oscillator in response to an on / off signal corresponding to an on state or an off state of the digital phase locked loop circuit and the reference clock signal. And a digital phase locked loop circuit. The method of claim 1, wherein the control unit, And applying the reference clock signal to the digitally controlled oscillator in response to the on / off signal corresponding to the on state of the digital phase locked loop circuit. The method of claim 1, wherein the control unit, Characterized in that the reference clock signal is input to the digitally controlled oscillator after the on / off signal corresponding to the on state of the digital phase locked loop circuit is applied and a predetermined time for frequency locking has elapsed. Digital phase locked loop circuit. The method of claim 1, wherein the control unit, And after the on / off signal corresponding to the on state of the digital phase locked loop circuit is applied and the reference clock signal passes one clock, the reference clock signal is inputted to the digitally controlled oscillator. Phase locked loop circuit. The method of claim 1, wherein the control unit, And apply one reference clock signal to the digital controlled oscillator in response to the on / off signal corresponding to the on state of the digital phase locked loop circuit. The method of claim 1, wherein the digital phase locked loop circuit, And a bandwidth controller for controlling a bandwidth of an output signal of the digital phase frequency detector. The method of claim 6, wherein the bandwidth control unit, And extending the bandwidth of the output signal of the digital phase frequency detector and reducing the bandwidth whenever the output signal of the digital phase locked loop circuit crosses the reference clock signal. The method of claim 6, wherein the bandwidth control unit, And controlling a bandwidth of an output signal of the digital phase locked loop circuit by controlling the digital loop filter. The method of claim 6, wherein the digital phase frequency detector, Digital phase locked loop circuit, characterized in that the Bang-Bang Phase Frequency Detector (Bang-Bang Phase Frequency Detector). The method of claim 6, wherein the bandwidth control unit, And the controller operates after applying the reference clock signal to the digitally controlled oscillator in response to the on / off signal corresponding to the on state of the digital phase locked loop circuit. The method of claim 1, wherein the control unit, The digital loop filter is turned off until the reference clock signal is applied to the digitally controlled oscillator, and the digital loop filter is turned on after the reference clock signal is applied to the digitally controlled oscillator. Digital phase locked loop circuit, characterized in that for controlling. The method of claim 1, wherein the digital phase locked loop circuit, And a divider for dividing the output signal and outputting the divided output signal to the digital phase frequency detector. The method of claim 12, wherein the control unit, The divider is controlled to be in an off state until the reference clock signal is applied to the digitally controlled oscillator, and the divider is controlled to be in an on state after the reference clock signal is applied to the digitally controlled oscillator. And a digital phase locked loop circuit. The method of claim 12, wherein the digital phase locked loop circuit, And a delay unit which delays the reference clock signal by the delay amount of the output signal by the divider and outputs the delayed reference clock signal to the digital phase frequency detector. The method of claim 1, wherein the digital phase locked loop circuit, And a DA converter for converting the digital control voltage signal into an analog form and outputting the analog voltage to the digital controlled oscillator. The method of claim 15, wherein the digital loop filter, A sub digital loop filter outputting a control voltage signal in response to an output signal of the digital phase frequency detector; A comparator for comparing the control voltage signal with an output signal of the DA converter; And a counter for counting an output signal of the comparator and outputting the digital control voltage signal. A method of controlling a digital phase locked loop circuit having a digitally controlled oscillator, Determining whether the digital phase locked loop circuit is on or off; And And applying a reference clock signal to the digitally controlled oscillator when the digital phase locked loop circuit is changed from an off state to an on state. The method of claim 1, wherein applying the reference clock signal comprises: And applying the reference clock signal to the digitally controlled oscillator after the digital phase locked loop circuit is changed from an off state to a on state and a predetermined time for frequency locking has elapsed. Control method of the circuit. The method of claim 1, wherein the control method of the digital phase locked loop circuit comprises: Comparing the reference clock signal with an output signal of the digital phase locked loop circuit, detecting a phase difference and a frequency difference, and outputting a digital phase frequency detection signal; And And controlling a bandwidth of the phase frequency detection signal. The method of claim 19, wherein controlling the bandwidth comprises: Extending the bandwidth of the phase frequency detection signal; And And reducing the bandwidth whenever the output signal of the digital phase locked loop circuit and the reference clock signal cross each other. The method of claim 19, wherein controlling the bandwidth comprises: And controlling a bandwidth of the phase frequency detection signal after applying a reference clock signal to the digitally controlled oscillator.

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