KR100990610B1 - Phase Detector - Google Patents

Abstract

According to an embodiment, a phase detector includes: a D-flip flop receiving a reference signal through a first terminal, a comparison signal through a second terminal, and outputting an output signal through a third terminal; One input terminal is connected to the third terminal, and the other input terminal includes a NAND gate configured to receive the reference signal; And an inverter for inverting and outputting the output signal of the NAND gate, wherein the phase comparison result is processed as an up signal.

According to the embodiment, since the phase detector can be implemented using the minimum number of circuit elements, the phase of the comparison signal and the reference signal can be quickly compared, the power consumption of the phase detector can be minimized, and the device size can be greatly reduced. have. In addition, since the phase is compared using only the rising edges of the comparison signal and the reference signal, the influence of the duty cycle of the comparison signal and the reference signal can be eliminated.

Phase Detectors, D-Flip-Flops, NAND Gates, Inverters, Polling Edges, Rising Edges

Description

Phase Detector

An embodiment relates to a phase detector.

Currently, various narrowband and broadband communication systems are being developed to provide services such as mobile communication, satellite communication, and broadcasting. Circuits constituting such communication systems, such as mixers, balloon circuits, modulators, demodulators, etc. The clock signal is needed to process the frequency signal.

The voltage controlled oscillation circuit configures a phase synchronization circuit to generate a clock signal. For example, the voltage controlled oscillation circuit may include a delay lock loop (DLL) and a phase clock generator. In addition, the DLL may include a phase detector, a charge pump, a loop filter, and a voltage controlled delay line (VCDL).

The VCDL receives a reference clock from an oscillation circuit such as a TCXO (Temperature controlled X-tal Oscillator) and generates a plurality of phase delay signals by generating a constant phase delay in the reference clock.

In this case, the phase detector receives the phase delay signals in order and compares them with a reference clock, and generates a control signal corresponding to the frequency difference between each phase delay signal and the reference clock. The charge pump adjusts the current value according to the control signal.

The charge pump adjusts the control voltage delivered to the VCDL by supplying or absorbing a certain amount of charge to the loop filter according to the control signal. Thus, the VCDL can generate a plurality of phase delay signals with precise intervals and pass them to the phase clock generator.

1 is a timing diagram schematically illustrating a signal form processed by a phase detector.

As shown in FIG. 1A, the phase detector compares the reference signal RCLK with the comparison signal, and generates a UP signal corresponding to the phase difference when the comparison signal phase is earlier than the phase of the comparison signal. .

As a result of comparison, as shown in (b), when the phase of the reference signal is slower than the phase of the comparison signal, a down (DN) signal corresponding to the phase difference is generated. Therefore, the phase detector can know the phase difference between the two frequency signals. For example, among the above examples of the voltage controlled oscillation circuit, the reference clock, the phase delay signal, and the control signal may correspond to the reference signal, the comparison signal, and the up / down signal, respectively.

However, in order to configure the phase detector operated as described above, a large number of circuit elements such as transistors and logic gates are required, and thus, power consumption is large and device size is large.

The embodiment can be implemented with a minimum number of circuit elements, and provides a phase detector capable of minimizing device size, power consumption, and operation time.

According to an embodiment, a phase detector includes: a D-flip flop receiving a reference signal through a first terminal, a comparison signal through a second terminal, and outputting an output signal through a third terminal; One input terminal is connected to the third terminal, and the other input terminal includes a NAND gate configured to receive the reference signal; And an inverter for inverting and outputting the output signal of the NAND gate, wherein the phase comparison result is processed as an up signal.

According to an embodiment, a phase detector includes a D-flip flop for receiving a comparison signal through a first terminal, a reference signal through a second terminal, and outputting an output signal through a third terminal; One input terminal is connected to the third terminal, and the other input terminal includes a NAND gate configured to receive the comparison signal; And an inverter for inverting and outputting the output signal of the NAND gate, wherein the phase comparison result is processed as a down signal.

According to the embodiment, the following effects are obtained.

First, since the phase detector can be implemented using the minimum number of circuit elements, the phase of the comparison signal and the reference signal can be quickly compared, power consumption of the phase detector can be minimized, and the device size can be greatly reduced.

Second, since the phase is compared using only the rising edges of the comparison signal and the reference signal, the influence of the duty cycle of the comparison signal and the reference signal can be excluded.

With reference to the accompanying drawings, a phase detector according to an embodiment will be described in detail.

Hereinafter, in describing the embodiments, detailed descriptions of related well-known functions or configurations are deemed to unnecessarily obscure the subject matter of the present invention, and thus only the essential components directly related to the technical spirit of the present invention will be referred to. .

2 is a block diagram schematically showing the configuration of the phase detector according to the first embodiment, and FIG. 3 is a circuit diagram schematically showing the configuration of the phase detector according to the first embodiment.

The first embodiment relates to a phase detector in the case of processing a phase comparison result as an UP signal.

Referring to FIG. 2, the phase detector according to the first embodiment includes a D-flip flop 110, a Nand gate 120, and an inverter 130. The flop 110 includes a first terminal a to which the reference signal RCLK is input, a second terminal b to which the comparison signal FCLK is input, and a third terminal c to which an output signal is output.

FIG. 3 illustrates a phase detector illustrated in FIG. 2 using a P-channel metal-oxide-semiconductor field-effect transistor (PMOS) and an N-channel metal-oxide-semiconductor field-effect transistor (NMOS).

Referring to FIG. 3, the phase detector according to the first embodiment includes nine transistors 111, 112, 113, 121, 122, 123, 124, 131, and 132.

The D-flip-flop 110 is a circuit for generating an output signal by delaying an input signal by a time interval of a clock pulse, and includes a first transistor 111 to a third transistor 113.

The drain of the first transistor 111 is connected to the drain of the second transistor 112 and the source of the second transistor is connected to the drain of the third transistor 113.

The NAND gate 120 includes a fourth transistor 121 to a seventh transistor 124, wherein the source and the drain of the fourth transistor 121 are respectively the source and the drain of the first transistor 111. It is connected to the drain of the fifth transistor 122.

In addition, the source of the fifth transistor 122 is connected to the drain of the sixth transistor 123, and the gates of the fourth transistor 122 and the sixth transistor 123 are the first transistor 111. It is connected to the drain of.

In addition, the source and the drain of the seventh transistor 124 are connected to the source and the drain of the fourth transistor 121, respectively.

The inverter 130 includes an eighth transistor 131 and a ninth transistor 132, and the source and the drain of the eighth transistor 131 are respectively the source and the seventh transistor 124. 9 is connected to the drain of the transistor 132.

In addition, the source of the ninth transistor 132 is connected to the source of the sixth transistor 123, and the gate of the eighth transistor 131 and the ninth transistor 132 is the seventh transistor 124. It is connected to the drain of.

In this configuration, the gates of the first transistor 111 and the third transistor 113 function as a first terminal a to which the reference signal RCLK is input, and the gate of the second transistor 112. 2 serves as the second terminal b to which the comparison signal FCLK is input.

The node between the drain of the first transistor 111 and the drain of the second transistor 112 functions as a third terminal c through which the output signal of the D-flip flop 110 is output.

The gate of the fifth transistor 122 and the gate of the seventh transistor 124 function as a terminal to which the reference signal RCLK is input among two input terminals of the NAND gate 120, and the fourth transistor ( 121 and the gate of the sixth transistor 123 function as a terminal connected to the third terminal (c) of the D-flip flop 110 of the two input terminals of the NAND gate (120).

The drain of the fifth transistor 122, the drain of the fourth transistor 121, and the drain of the seventh transistor 124 function as an output terminal of the NAND gate 120.

In addition, the gates of the eighth transistor 131 and the ninth transistor 132 function as an input terminal of the inverter 130, and the drain of the eighth transistor 131 and the ninth transistor 132 The nodes between the drains serve as output terminals of the inverter 130, that is, final output terminals of the phase detector according to the first embodiment.

In the first embodiment, the first transistor 111, the fourth transistor 121, the seventh transistor 124 and the eighth transistor 131 is provided with a PMOS, the second transistor 112 The third transistor 113, the fifth transistor 122, the sixth transistor 123, and the ninth transistor 132 are provided as NMOSs.

The operation of the phase detector according to the first embodiment having the configuration as described above is as follows.

The first operation is that the rising edge of the reference signal RCLK is faster than the rising edge of the comparison signal FCLK, and the falling edge of the comparison signal FCLK is faster than the falling edge of the reference signal RCLK. It's a quick case.

FIG. 4 is a timing diagram schematically illustrating a signal form processed by the phase detector according to the first embodiment.

In the “A” section of FIG. 4, since the reference signal RCLK is low, the seventh transistor 124 is turned on and the drain of the seventh transistor 124 (the NAND gate Output terminal 120) becomes high. Accordingly, the output terminal of the inverter 130 is reset to low potential regardless of the level of the comparison signal FCLK.

In the section “B” of FIG. 4, since the reference signal RCLK has a high potential, the drain (third terminal c) of the first transistor 111 is maintained at a high potential. The fifth transistor 122 is operated so that the drain (output terminal of the NAND gate 120) of the fifth transistor 122 becomes low potential. Therefore, the output terminal of the inverter 130 is switched to the high potential regardless of the level of the comparison signal FCLK.

In the “C” section of FIG. 4, since the reference signal RCLK and the comparison signal FCLK are both high potentials, the second transistor 112 and the third transistor 113 are operated, and the second transistor is operated. The drain (third terminal c) of 112 becomes low potential.

At this time, since the fifth transistor 122 is operating, the drain of the fifth transistor (the output terminal of the NAND gate 120) becomes a high potential, and the output terminal of the inverter 130 has a low potential. do.

In the “D” section of FIG. 4, since the comparison signal FCLK is switched to the low potential, the drain of the second transistor 112 (the third terminal c) is maintained at the low potential, and the NAND gate 120 The output terminal of the high potential, the output terminal of the inverter 130 is maintained at a low potential.

Thereafter, the operation of the phase detector according to the section "A" to "D" of FIG. 4 may be repeated.

The second operation is when both the rising edge and the falling edge of the reference signal RCLK are faster than the rising edge and the falling edge of the comparison signal FCLK.

FIG. 5 is a timing diagram schematically illustrating a signal form processed by the phase detector according to the first embodiment.

In the section “A” of FIG. 5, since the reference signal RCLK is low, the seventh transistor 124 is turned on and the drain of the seventh transistor 124 (the NAND gate Output terminal 120) becomes high. Accordingly, the output terminal of the inverter 130 is reset to low potential regardless of the level of the comparison signal FCLK.

In the " B " section of FIG. 5, since the reference signal RCLK has a high potential, the drain (third terminal c) of the first transistor 111 is maintained at a high potential. The fifth transistor 122 is operated so that the drain (output terminal of the NAND gate 120) of the fifth transistor 122 becomes low potential. Therefore, the output terminal of the inverter 130 is switched to the high potential regardless of the level of the comparison signal FCLK.

In the “C” section of FIG. 5, since the reference signal RCLK and the comparison signal FCLK are both high potentials, the second transistor 112 and the third transistor 113 are operated to operate the second transistor. The drain (third terminal c) of 112 becomes low potential.

At this time, since the fifth transistor 122 is operating, the drain of the fifth transistor (the output terminal of the NAND gate 120) becomes a high potential, and the output terminal of the inverter 130 has a low potential. do.

In the “D” section of FIG. 5, since the reference signal RCLK is switched to the low potential while the comparison signal FCLK is at high potential, the seventh transistor 124 is turned on and the seventh transistor is turned on. A drain 124 (the output terminal of the NAND gate 120) becomes a high potential. Accordingly, the output terminal of the inverter 130 is reset to low potential regardless of the level of the comparison signal FCLK.

Thereafter, the operation of the phase detector according to the section "A" to "D" of FIG. 5 may be repeated.

In a third operation, the rising edge of the reference signal RCLK is slower than the rising edge of the comparison signal FCLK, and the falling edge of the comparison signal FCLK is lower than the falling edge of the reference signal RCLK. It is a slow case.

FIG. 6 is a timing diagram schematically illustrating a signal form processed by the phase detector according to the first embodiment.

In the section “A” of FIG. 6, since the reference signal RCLK is low, the seventh transistor 124 is turned on and the drain of the seventh transistor 124 (the NAND gate Output terminal 120) becomes high. Accordingly, the output terminal of the inverter 130 is reset to low potential regardless of the level of the comparison signal FCLK.

In the " B " section of FIG. 6, the comparison signal FCLK is switched to the high potential, and the reference signal RCLK is low potential, so that the seventh transistor 124 is operated and the seventh transistor 124 is operated. The drain of (the output terminal of the NAND gate 120) becomes a high potential. Therefore, the output terminal of the inverter 130 maintains a low potential regardless of the level of the comparison signal FCLK.

In the “C” section of FIG. 6, since the reference signal RCLK and the comparison signal FCLK are both high potentials, the second transistor 112 and the third transistor 113 are operated to operate the second transistor. The drain (third terminal c) of 112 becomes low potential.

At this time, since the fifth transistor 122 is operating, the drain of the fifth transistor (the output terminal of the NAND gate 120) becomes a high potential, and the output terminal of the inverter 130 has a low potential. Keep it.

In the “D” section of FIG. 6, since the reference signal RCLK is switched to the low potential while the comparison signal FCLK is at high potential, the seventh transistor 124 is operated and the seventh transistor 124 is operated. The drain of (the output terminal of the NAND gate 120) becomes a high potential. Therefore, the output terminal of the inverter 130 maintains a low potential regardless of the level of the comparison signal FCLK.

Thereafter, the operation of the phase detector according to the section "A" to "D" of FIG. 6 may be repeated.

The fourth operation is when both the rising edge and the falling edge of the reference signal RCLK are slower than the rising edge and the falling edge of the comparison signal FCLK.

7 is a timing diagram schematically illustrating a signal form processed by the phase detector according to the first embodiment in the fourth case.

In the “A” section and the “B” section of FIG. 7, since the reference signal RCLK is low, the seventh transistor 124 is turned on and the drain of the seventh transistor 124 is turned on. (The output terminal of the NAND gate 120) becomes a high potential. Accordingly, the output terminal of the inverter 130 is reset to low potential regardless of the level of the comparison signal FCLK.

In the “C” section of FIG. 7, since the reference signal RCLK and the comparison signal FCLK are both high potentials, the second transistor 112 and the third transistor 113 are operated, and the second transistor is operated. The drain (third terminal c) of 112 becomes low potential.

At this time, since the fifth transistor 122 is operating, the drain of the fifth transistor (the output terminal of the NAND gate 120) becomes a high potential, and the output terminal of the inverter 130 has a low potential. Keep it.

In the " D " section of FIG. 7, since the comparison signal FCLK is switched to the low potential while the reference signal RCLK is at a high potential, the operations of the first transistor 111 and the second transistor 112 are both performed. It is turned off.

Accordingly, the drain (third terminal c) of the first transistor 111 and the second transistor 112 is maintained at a low potential, and accordingly, the fourth transistor 121 and the fifth transistor 122 are maintained. Also, the drain of the seventh transistor 124 (the output terminal of the NAND gate 120) and the drain of the eighth transistor 131 and the ninth transistor 132 (the output terminal of the inverter 130) are also low potential. Maintain state.

Thereafter, the operation of the phase detector according to the section "A" to "D" of FIG. 7 may be repeated.

Hereinafter, a phase detector according to a second embodiment will be described with reference to the accompanying drawings. The second embodiment relates to a phase detector in the case of processing a phase comparison result as a DOWN signal.

8 is a block diagram schematically showing the configuration of the phase detector according to the second embodiment, and FIG. 9 is a circuit diagram schematically showing the configuration of the phase detector according to the second embodiment.

Referring to FIG. 8, the phase detector according to the second embodiment includes a D-flip flop 210, a Nand gate 220, and an inverter 230. The flop 210 includes a second terminal b to which the reference signal RCLK is input, a first terminal a to which the comparison signal FCLK is input, and a third terminal c to which an output signal is output.

FIG. 9 implements the phase detector shown in FIG. 8 using PMOS and NMOS.

Referring to FIG. 9, the phase detector according to the second embodiment includes nine transistors 211, 212, 213, 221, 222, 223, 224, 231, and 232.

When comparing the second embodiment shown in Figs. 8 and 9 with the first embodiment shown in Figs. 1 and 2, the first terminal (a) of the D-flip flop 110 in the case of the first embodiment While the reference signal RCLK and the comparison signal FCLK are input to the second terminal b and the second terminal b, respectively, in the second embodiment, the first terminal a and the second terminal of the D-flop flop 210 b) The difference between the input of the comparison signal FCLK and the reference signal RCLK is different.

In addition, one input terminal of the NAND gate 220 is connected to the output terminal of the D-flip flop 210, and the other input terminal is different from the first embodiment in that the comparison signal FCLK is input. Do.

The connection relations and operations of the components of the second embodiment are the same as those of the first embodiment.

10 to 13 are timing diagrams schematically illustrating signal types processed by the phase detector according to the second embodiment, and FIGS. 10 to 13 correspond to FIGS. 4 to 7, respectively.

That is, FIG. 10 shows that the rising edge of the reference signal RCLK is faster than the rising edge of the comparison signal FCLK, and the falling edge of the comparison signal FCLK is the falling edge of the reference signal RCLK. In a faster first case, a timing diagram schematically illustrating a signal type processed by the phase detector according to the second embodiment, and FIG. 11 shows that both the rising edge and the falling edge of the reference signal RCLK are the rising edge of the comparison signal FCLK In the second case, which is faster than the falling edge, the timing diagram schematically illustrating the signal form processed by the phase detector according to the second embodiment.

12 shows that the rising edge of the reference signal RCLK is slower than the rising edge of the comparison signal FCLK, and the falling edge of the comparison signal FCLK is the falling edge of the reference signal RCLK. In a slower third case, a timing diagram schematically illustrating a signal type processed by the phase detector according to the second embodiment is shown. In FIG. In the fourth case slower than the falling edge, it is a timing diagram schematically illustrating the signal form processed by the phase detector according to the second embodiment.

The operations of the second embodiment of FIGS. 10 to 13 are compared with those of FIGS. 4 to 7, and the types of signals input to the first terminal a and the second terminal b and the NAND gates 120 and 220. It can be seen that the types of signals input to the one input terminal of are different and only the output signal is processed as the down signal, but the other signal processing results are the same.

Therefore, the description of the second embodiment which is repeated below with the first embodiment will be omitted.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications other than those described above are possible. For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a timing diagram schematically illustrating a signal form processed by a phase detector.

Fig. 2 is a block diagram schematically showing the configuration of the phase detector according to the first embodiment.

3 is a circuit diagram schematically showing the configuration of the phase detector according to the first embodiment;

4 to 7 are timing diagrams schematically illustrating signal types processed by the phase detector according to the first embodiment.

8 is a block diagram schematically showing the configuration of a phase detector according to the second embodiment;

9 is a circuit diagram schematically showing the configuration of a phase detector according to the second embodiment.

10 to 13 are timing diagrams schematically illustrating signal types processed by the phase detector according to the second embodiment.

Claims (11)

delete delete A D-flip flop that receives a reference signal through a first terminal, receives a comparison signal through a second terminal, and outputs an output signal through a third terminal; One input terminal is connected to the third terminal, and the other input terminal includes a NAND gate configured to receive the reference signal; And An inverter for inverting and outputting an output signal of the NAND gate, Process the phase comparison result as an up signal, The D flip-flop includes a first transistor and a second transistor connected to drains of each other, a third transistor connected to a source of the second transistor and its drain, The NAND gate may include a fourth transistor having a source and a gate connected to a source and a drain of the first transistor, and a sixth transistor having a source and a gate connected to a source of the third transistor and a drain of the first transistor, respectively. A fifth transistor having a source connected to the drain of the fourth transistor and a drain of the sixth transistor, and a seventh transistor having a source and a drain connected to the source and the drain of the fourth transistor, respectively, The inverter may include: an eighth transistor having a source and a gate connected to the source and the drain of the seventh transistor; Phase detector comprising a. The method of claim 3, Gates of the first transistor and the third transistor function as the first terminal, gates of the second transistor function as the second terminal, and the drain of the first transistor and the drain of the second transistor are the first. Function as three terminals, Gates of the fifth and seventh transistors serve as reference signal input terminals of the NAND gate, and drains of the fifth transistor, the fourth transistor, and the seventh transistor serve as output terminals of the NAND gate. , And the drains of the eighth and ninth transistors function as output terminals of the inverter. A D-flip-flop that receives a comparison signal through a first terminal, receives a reference signal through a second terminal, and outputs an output signal through a third terminal; One input terminal is connected to the third terminal, and the other input terminal includes a NAND gate configured to receive the comparison signal; And An inverter for inverting and outputting an output signal of the NAND gate, The phase comparison result is processed as a down signal. The D flip-flop includes a first transistor and a second transistor connected to drains of each other, a third transistor connected to a source of the second transistor and its drain, The NAND gate may include a fourth transistor having a source and a gate connected to a source and a drain of the first transistor, and a sixth transistor having a source and a gate connected to a source of the third transistor and a drain of the first transistor, respectively. A fifth transistor having a source connected to the drain of the fourth transistor and a drain of the sixth transistor, and a seventh transistor having a source and a drain connected to the source and the drain of the fourth transistor, respectively, The inverter may include: an eighth transistor having a source and a gate connected to the source and the drain of the seventh transistor; Phase detector comprising a. The method of claim 5, Gates of the first transistor and the third transistor function as the first terminal, gates of the second transistor function as the second terminal, and the drain of the first transistor and the drain of the second transistor are the first. Function as three terminals, Gates of the fifth and seventh transistors serve as comparison signal input terminals of the NAND gate, and drains of the fifth transistor, the fourth transistor, and the seventh transistor serve as output terminals of the NAND gate. , And the drains of the eighth and ninth transistors function as output terminals of the inverter. The method according to claim 3 or 5, The first transistor, the fourth transistor, the seventh transistor and the eighth transistor are provided as PMOS, And the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the ninth transistor are each provided with NMOS. The method according to claim 3 or 5, If the rising edge of the reference signal is faster than the rising edge of the comparison signal, the falling edge of the comparison signal is faster than the falling edge of the reference signal, The output terminal of the inverter becomes low potential in a section where the reference signal and the comparison signal are low potential, a section where the reference signal and the comparison signal are high potential, and a section where the reference signal is low potential and the comparison signal is high potential, And the output terminal of the inverter becomes a high potential in a section in which the reference signal is high potential and the comparison signal is low potential. The method according to claim 3 or 5, When both the rising edge and the falling edge of the reference signal are faster than the rising edge and the falling edge of the comparison signal, In the section where the reference signal and the comparison signal is low potential, the section where the reference signal is low potential and the comparison signal is high potential, and the section where the reference signal and the comparison signal are high potential, the output terminal of the inverter becomes low potential, And the output terminal of the inverter becomes high potential in a section in which the reference signal is high potential and the comparison signal is low potential. The method according to claim 3 or 5, When the rising edge of the reference signal is slower than the rising edge of the comparison signal, and the falling edge of the comparison signal is slower than the falling edge of the reference signal, The output terminal of the inverter maintains a low potential in a section in which the reference signal and the comparison signal are low potential, a section in which the reference signal is low potential and the comparison signal is high potential, and a section in which the reference signal and the comparison signal are high potential. Characterized by a phase detector. The method according to claim 3 or 5, When both the rising edge and the falling edge of the reference signal are slower than the rising edge and the falling edge of the comparison signal, A section in which the reference signal and the comparison signal are low potential, a section in which the reference signal is low potential and the comparison signal is high potential, a section in which the reference signal and the comparison signal are high potential, the reference signal is high potential and the comparison signal is Phase detector characterized in that the output terminal of the inverter maintains a low potential in a low potential section.

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