JP2012049659A - Digital phase lock loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a configuration of an ADPLL which can be used for a deskew application, without enlarging the circuit scale of a TDC(Time-to-Digital Converter).SOLUTION: The digital phase lock loop circuit includes a DCO 19, an MDIV 11 which divides an FREF, a PDIV 20 which divides an output FO of the DCO, an NDIV 12 which divides an output FOUT of the PDIV, a TDC 13 which measures a phase difference between an output signal FR of the MDIV and the output FO of the DCO, a TDC 14 which measures a phase difference between an output FD of the NDIV and the FO, an FF 15 which samples the FO with the FR, a CONT 17 which counts the FO during the period between the edges of a pulse of the FR or the FD having a preceeding phaze and the next pulse, a PERR 16 which inputs the outputs of the TDCs 13 and 14 and the FF 15 thereinto and receives an output of a counter to calculate a phase difference between the FR and the FD, and a DFIL 18 which inputs the output of PERR thereinto and supplies a signal that has been filtered to the DCO.

Description

  The present invention relates to a phase-locked loop circuit, and more particularly to a digital phase-locked loop circuit suitable for application to an ADPLL (All Digital Phase Locked Loop) for deskew (De-Skew).

  In recent years, an analog PLL (Phase Locked Loop) (PLL macro) incorporated as a clock generation circuit in a semiconductor integrated circuit device such as an application specific integrated circuit (ASIC) (ASIC) has an analog element such as a resistor or a capacitor. Various problems have been faced, such as an increase in area due to the use and configuration, and deterioration of characteristics due to a decrease in power supply voltage (lower voltage). Therefore, development of an all-digital PLL (ADPLL) in which all elements of the analog PLL are replaced with a digital configuration has been actively promoted.

  FIG. 14 shows an example of a typical configuration of a multiplication analog PLL (APLL). As shown in FIG. 14, this PLL includes a pre-stage divider (MDIV) 31 that divides a reference clock (reference clock) signal FREF input to the FREF terminal by M, and an output of the pre-stage divider (MDIV) 31. A phase frequency comparator (PFD) 33 that receives the signal FR and the output signal FD of the feedback frequency divider (NDIV) 32 and compares the phase and frequency, and the phase comparison result UP / DN in the phase frequency comparator (PFD) 33 An analog filter comprising a charge pump (CP) 34 for controlling the current for charging / discharging the capacity in accordance with the voltage and storing a voltage corresponding to the phase difference, and a low-pass filter for smoothing the voltage of the charge pump (CP) 34 (FIL) 35 and the output voltage of analog filter (FIL) 35 are input as control voltages, and an oscillation clock having a frequency corresponding to the control voltage is output. A voltage-controlled oscillator (VCO) 36, a post-stage divider (PDIV) 37 that outputs a signal FOUT obtained by dividing the output clock signal FO of the voltage-controlled oscillator (VCO) 36 by P, and an output of the voltage-controlled oscillator (VCO) 36 A feedback frequency divider (NDIV) 32 that outputs a signal FD obtained by dividing the clock signal FO by N, a signal FR (frequency: FREF / M) obtained by dividing the reference clock signal FREF by M, and a voltage controlled oscillator ( Control is performed so that the phase and frequency of the signal FD (frequency: (FOUT × P) / N) obtained by dividing the output clock signal FO (frequency: FOUT × P) of the VCO 36 by N are the same.

  FREF / M = (FOUT × P) / N (1)

  FREF, FR, FD, FO, FOUT, etc. are a reference clock signal, a reference clock signal divided by M, a feedback clock signal obtained by dividing FOUT by N, an oscillation clock signal, and an output clock signal obtained by dividing DO by P. Although each signal is represented, it is assumed that the frequency of each signal is represented.

From the above equation (1), the multiplication analog PLL outputs the frequency FOUT of the following equation (2).
FOUT = FREF × N / (M × P) (2)

  Therefore, the total multiplied value is given by the following equation (3) from FOUT / FREF.

  N / (M × P) (3)

  The multiplication analog PLL has a feedback path (feedback path) in the PLL circuit, and outputs a multiplied clock (frequency FOUT).

  On the other hand, the De-skew analog PLL includes a feedback path (feedback path) outside the PLL circuit, and matches the phases of the reference clock signal and the feedback clock signal (feedback clock).

  FIG. 15 shows an example of a typical configuration of an analog PLL for De-skew. This analog PLL for De-skew is a macro used for phase matching of input / output signals between chips and between macros. For this reason, a CTS (Clock Tree Synthesis) 41 is arranged in a feedback path (feedback path) outside the PLL 30. A buffer (CTS buffer) is inserted into the CTS 41 so as to eliminate skew between terminals in the clock distribution system. Feedback control is performed so that the phase and frequency of the signal FR obtained by dividing the reference clock signal FREF by M and the signal FD obtained by dividing the signal FBAK output from the terminal of the CTS 41 by N are the same.

  FREF / M = FOUT / N (4)

  The De-Skew analog PLL outputs a frequency FOUT represented by the following equation (5).

  FOUT = FREF × N / M (5)

Therefore, the total multiplication value is
N / M
It is.

  FIG. 16 is a diagram schematically showing an example of an application example of the De-Skew analog PLL 30 shown in FIG. 15 (FIG. 16 is drawn by the inventor of the present application). As shown in FIG. 16, the De-Skeke PLL 30 (equivalent to the De-Skew analog PLL 30 in FIG. 16) is used, for example, when data is exchanged between different clock domains or between chips. Data can be exchanged by adjusting the phases of the ends of the CTSs 41 and 42 and synchronizing them. In the example shown in FIG. 16, the clock input to the FREF terminal of the De-Skeke PLL 30 is input to the user logic 43 operating at 200 MHZ, and the output clock from the FOUT terminal of the De-Skeke PLL 30 is passed through the CTS 41. The signal is input to the user logic 44 operating at 400 MHZ and input to the terminal FBAK, and is controlled so that the phases of the rising edges of the two signals FREF and FBAK are aligned in the PLL 30 for De-Skew.

  When applying the configuration of ADPLL to the above-described PLL 30 for De-Skew, it became clear that there is a problem as described below (according to the analysis of the present inventors). In the following, ADPLL will be described first as a premise for explaining this problem.

  FIG. 17 is a diagram illustrating a configuration of the ADPLL disclosed in Patent Document 1. FIG. 18 is a simplified diagram of FIG. 17 (see FIG. 1 of Non-Patent Document 1). As shown in FIG. 18, a reference clock signal FREF is input to a time-to-digital converter (TDC) 1 and a flip-flop (FF) that inputs an output CKV of a digitally-controlled-oscillator (DCO) to a clock terminal. ) 2 is input to the data terminal. The FF 2 samples the FREF in response to the rising edge of the CKV, and outputs the timing-adjusted FREF (Retimed FREF) as CKR (Retimed FREF). CKR is input to a latch circuit (Latch) that latches the measurement result of TDC 1 and an accumulator (Reference Phase Accumulator) 3. The accumulator 3 accumulates (accumulates) the multiplication set value every time the CKR edge is input.

  In FIG. 18, TDC1 (corresponding to 201 in FIG. 17) outputs the difference between the phase of the FREF and the phase of the output clock CKV at the timing of the reference clock signal FREF as digital data. This phase difference corresponds to the number of delay elements in TDC1.

  FIG. 24 shows a configuration example of the TDC 201 shown in FIG. The TDC receives the DCO output CKV and the reference clock FREF, and outputs the phase difference TDC_RISE between the rising edge of CKV and the rising edge of FREF, and the phase difference TDC_FALL between the falling edge of CKV and the rising edge of FREF. As shown in FIG. 24, the TCD 1 includes L delay elements, L FFs, and an edge detector.

  FIG. 25 is a diagram showing the timing operation of the TDC of FIG. 24, where L = 10. At TDC, signals D (0) to D (L-1) obtained by gradually delaying the output CKV of the DCO with L delay elements are sampled at the rising edge of the reference clock signal FREF at time T1. For example, “0011110000” is obtained as the bit sampling data Q [0: 9]. By detecting a location where the value changes from 0 to 1 and a location where the value changes from 1 to 0 in the sampling data Q [0: 9], the interval between the rising edge and the falling edge of the delayed output clock CKV is determined. , And can be expressed by the number of stages of delay elements. In this case, the location Q [6] that changes from 1 to 0 becomes the information of the rising edge (Q [2-5] is 1 and becomes 0 at Q [6]), and the location Q that changes from 1 to 0 [2] is falling edge information (Q [6-9], Q [0-1] is 1 and Q [2] is 1), which are output as digital data TDC_RISE and TDC_FALL, respectively. . That is, the rising edge of the output clock CKV is advanced by 6 stages of delay elements in the TDC with respect to the rising edge of FREF by the TDC, and the falling edge of the output clock CKV is delayed in the TDC with respect to the rising edge of FREF. It is measured that it has advanced two stages.

  In the ADPLL of FIGS. 18 and 17, TDC1 (TDC201) only needs to be able to measure the time for one period of the maximum CKV signal. The output of TDC1 (TDC201) is input to a DCO period normalization circuit 5, and the phase difference corresponding to the number of delay elements measured by TDC1 is set to a ratio (decimal part) to one period of CKV. Normalized.

  An accumulator (Oscillator Phase Accumulator) 4 accumulates (accumulates) the number of CKV edges (for example, rising edge), and outputs an accumulated value for each CKR timing (for example, rising edge timing). Through the above operation, the FREF accumulation value by the accumulator 3, the CKV accumulation value by the accumulator 4, and the phase difference (measured by TDC1) between FREF and CKV are obtained at each CKR timing. .

  The difference between the accumulator values of the accumulators 3 and 4 (RR [k] −Rv [k]) corresponds to a component representing the phase difference of one cycle or more of the output clock signal CKV of the DCO as an integer (for how many clock cycles) To show) On the other hand, the phase difference ε [k] obtained by TDC1 is a phase difference within one cycle of the output clock signal CKV of the DCO, and is treated as a decimal. RR [k], Rv [k], and ε [k] (k = 1, 2,...) Represent time discrete signals (signals sampled by the sampling clock CKR). The amplitude is also a discrete value (digital signal).

  From the obtained data, the phase error detection circuit (Phase detector) 6 outputs phase error data φE [k] by digital arithmetic processing according to the following equation (6).

  φE [k] = RR [k] −Rv [k] + ε [k] (6)

Where φE [k] is the phase difference (phase error data),
RR [k] is the accumulated value of FREF,
Rv [k] is the output of the sampler 8 (accumulated value of CKV),
ε [k] is phase difference data within CKV1 clock.

  The phase error data φE [k] is input to a digital filter (Loop Filter), smoothed, and DCO gain normalization (DCO gain normalization) is performed. Is input to the DCO. The DCO is composed of an LC resonance circuit, and the capacitance is varied by controlling the varicap diodes connected in parallel with the logic 1 and 0 voltages of each bit of the digital signal d [k], thereby varying the LC resonance frequency. Finally, the oscillation frequency of the DCO is adjusted (becomes locked) so that the phase error data φE [k] becomes zero.

  19A is a diagram showing the correspondence between the output Rv [i] of the accumulator 4 and the output clock CKV in FIG. 18 (see FIG. 5 of Non-Patent Document 1). FIG. 19B is a diagram illustrating a correspondence between the output RR [k] of the accumulator 3 and the clock CKR. Both are modulo 16, and the accumulation result takes a value of 0-15. FIG. 5 illustrates φE = 3, but in FIG. 19, φE = 0 (phase error = 0).

  As shown in FIG. 19A, the output Rv [i] of the accumulator 4 increases by modulo 16, one per pulse of the output clock CVK. Although Rv [i] (i = 1, 2,...) Also represents a time discrete signal, it is sample value data updated at the timing of CKV. The sampler 8 samples the output Rv [i] of the accumulator 4 at the timing of CKR, and the sampled signal Rv [k] is input to the phase error detection circuit (Phase detector) 6. The phase difference ε [k] (sampled at the timing of CKR) between FREF and CKV that falls within one cycle of CKV is also used for phase comparison in the phase error detection circuit (Phase detector) 6.

  As shown in FIG. 19B, when FCW (Frequency Command Word) = 10 is set for the accumulator 3 by the frequency setting command, the output RR [k] of the accumulator 3 is 10 for each CKR1 pulse. Increase by modulo 16.

  In the ADPLL shown in FIG. 18, a comparison operation (φE [k] = RR [k] −Rv [k] + ε [k]) is performed at the timing of CKR so that the difference φE [k] becomes zero. To do. The final phase comparison characteristics (input phase difference (CKV number) and output digital code) are as shown in FIG. 20 (by the inventors of the present application). The fractional part of the phase difference within CKV1 clock cycle is set by the time resolution of the delay element in TDC1.

  In ADPLL, a configuration is also known in which an integer difference is measured by a counter instead of an accumulator (see, for example, Patent Document 2). FIG. 21 shows the configuration of the ADPLL disclosed in Patent Document 2 (FIG. 4 of Patent Document 2). As shown in FIG. 21, the PFD (Phase Frequency Detector) + TDC includes a delay line 401, a control logic circuit 402, a sampler 403, a counter 404, an adder 405, and an offset control circuit 406. The frequency divider DIV includes a prescaler 407, a program counter 408, and a swallow counter 409. The DLF has a digital filter (loop filter) and the DCO (Digitally-Controlled-Oscillator) has the same configuration as that shown in FIG.

  In the circuit of FIG. 21, as shown in FIG. 18, the integer part of the phase difference between the signals FREF and CKV is obtained not by the difference between the values of the two accumulators 3 and 4 but by the count value of the counter 404. The counter 404 receives the output of the sampler 403 that samples the reference signal VREF at the output VPRE (1 GHz) of the prescaler 407 of the frequency divider DIV, starts counting the VPRE, and outputs the program counter 408 of the frequency divider DIV. In response to VDIV (26 MHz), the count operation of the output VPRE of the prescaler 407 is stopped. This configuration locks in a state where VREF and VDIV have a phase difference due to the use of the counter 404 and the improvement of the TDC characteristics.

Japanese Patent Laid-Open No. 2002-076886 JP 2009-268047 A

Robert Bogdan Staszewski and Poras T. Balsara, "Phase-Domain All-Digital Phase-Locked Loop", IEEE TRANSACTION ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, PP.159-163, VOL.52, NO.3, MARCH 2005

  The analysis of related technology is given below.

  When the above ADPLL is applied to a De-skew PLL, there are the following problems.

  FIG. 22 is a diagram illustrating a configuration of a De-Skew PLL using the configuration of FIG. FIG. 22 is created by the present inventors for the purpose of explaining the problem.

  In general, the post-stage divider (PDIV) of the De-SkeW PLL can divide the frequency by about 1-16. The FBAK that is the output of the terminal (Leaf) of CTS (Clock Tree Synthesis) is inputted with a signal divided by 1 to 16 of the output clock signal CKV of the DCO. In FIG. 22, if the division value of the post-stage divider (PDIV) is 1, there is no problem because the operation is the same as the circuit of FIG. 18, but the division value of the post-stage divider (PDIV) is 1. If greater than, problems arise.

  In FIG. 22, an accumulator (Oscillator Phase Accumulator) 4 does not output the DCO output clock signal CKV but a signal FOUT obtained by frequency-dividing the DCO output clock signal CKV by the post-stage frequency divider (PDIV). The output signal at the end of the CTS is input to the FBAK terminal of the PLL.

  In the configuration of FIG. 18, the accumulator 4 accumulates (accumulates) every edge of the output clock CKV (2.4 GHz) of the DCO, but in FIG. 22, a signal (feedback path) input to the FBAK terminal. The signal output from the end of the CTS of the CTS has an edge (rising edge) only at the timing when the output CKV of the DCO is divided by P by the post-stage divider (PDIV). If the same processing as that in Fig. 18 is performed, the accumulator 4 needs to accumulate the P value (frequency-divided value) instead of 1 in response to the input of the FBAK edge. The configuration will be scaled up.

  Further, TDC1 is a problem. In the configuration of FIG. 18, the TDC 1 measures the phase difference within one period of the output clock CKV, and therefore includes only the number of delay elements and latch circuits (flip-flops) corresponding to the length capable of measuring one period of the CKV. Is enough. On the other hand, in the configuration of FIG. 22, in order to measure the phase difference within the period of P (P is an integer of 1 to 16) of the output clock signal CKV of the DCO, The latch circuit (flip-flop) is required up to 16 times that when the frequency division value is 1, which increases the circuit area of the TDC and causes a great disadvantage.

  FIG. 23 is a diagram showing the phase comparison characteristics of the input phase (phase difference between FREF and FBAK) and the output digital code (output of Phase Detector 5) in the configuration of FIG. When FIG. 23 is compared with FIG. 20, in FIG. 20, the TDC measures the length of one CKV period with a predetermined delay resolution. In FIG. 23, the TDC measures the CKVP period with a predetermined resolution. It is necessary to measure, and the length of the delay element array and the number of latch circuits (flip-flops) in the TDC of FIG.

  More specifically, in FIG. 22, when the post-stage divider (PDIV) is set to divide by 4 (P = 4), the accumulator 4 for accumulating FBAK has a period four times CKV (divide by 4). Therefore, all phase differences within 4 CKV clocks must be measured by TDC1. Similarly, when the frequency division number of the post-stage divider PDIV is set to 16 division (P = 16), it is necessary to measure CKV16 clocks at TDC1. If a further frequency division setting is possible, a delay element array and a latch circuit group that are long enough to measure the amount in TDC 1 are required.

  Therefore, with this ADPLL configuration, it is difficult and practically impossible to adopt a De-Skew PLL configuration.

  Also, the configuration shown in FIG. 21 cannot be used as a De-skew PLL. As shown in FIG. 21, the offset control circuit 406 for giving an offset gives a constant offset value to the phase error data. Therefore, at the time of locking, VREF and VDIV are locked with a difference corresponding to the phase data. Even without this offset function, the integer part of the phase difference counted by the counter 404 operates only with the clock after frequency division, as in the above-described ADPLL. Therefore, in order to interpolate the time for one period of the divided clock, it is necessary to extend the TDC measurement time. Therefore, for the same reason as described above, the configuration of FIG. 21 is also unsuitable for use as a De-Skew PLL.

  As described above, when the De-skew PLL is configured, the related art configuration is such that the signal of the post-stage divider (PDIV) is input to the accumulator, counter, and TDC, and therefore the phase difference measurement range at the TDC. Needs to be expanded in accordance with the divided value of the post-stage divider (PDIV) that divides the output CKV of the DCO by P, resulting in an increase in circuit scale and the like.

  Therefore, an object of the present invention is to provide a digital phase-locked loop circuit that can be used for deskewing without expanding the circuit scale of the TDC.

  The outline of the present invention will be described below. In addition, the code | symbol in the parenthesis attached | subjected to each element is for making an understanding of this invention easy, and of course should not be interpreted in order to restrict | limit this invention.

  According to the present invention, the effective edge (rising edge) of the clock signal whose phase is advanced among the input first clock signal (FR) and second clock signal (FD) is delayed in phase. A counter (17) for counting the number of valid edges (rising edges) of the third clock signal (FO) between valid edges (rising edges) of the clock signal that is present (time period); A first position for measuring a phase difference between effective edges of one clock signal (FR) and the third clock signal (FO) with a time resolution shorter than one cycle of the third clock signal (FO). The phase difference between the effective edges of the phase difference detection circuit (13) and the second clock signal (FD) and the third clock signal (FO) is shorter than one cycle of the third clock signal (FO). A second phase difference detection circuit (14) that measures with a time resolution between, a determiner (15) that determines which of the first clock signal and the second clock signal is advanced, Based on the output of the counter (17), the outputs of the first and second phase difference detection circuits (13, 14), and the output of the determiner (15), the first clock signal and the first A phase error calculator (16) for calculating the phase error of the second clock signal, and a digitally controlled oscillator (19) for varying the oscillation frequency based on the digital signal corresponding to the phase error and outputting the third clock signal , And the second clock signal (FD) is generated from a signal (FBAK) obtained by dividing the third clock signal (FO).

In the digital phase locked loop according to the present invention, a first frequency divider (11) that inputs and divides a reference clock signal;
A digitally controlled oscillator (19) that varies the oscillation frequency in accordance with the input digital signal;
A second frequency divider (20) for inputting and dividing the output signal (FO) of the digitally controlled oscillator (19) and outputting an output clock signal (FOUT);
A third frequency divider (12) for inputting and dividing a signal (FBAK) obtained by feeding back the output clock signal (FOUT) of the second frequency divider (20);
The output signal (FR) of the first frequency divider (11) and the output signal (FO) of the digitally controlled oscillator (19) are input, and the output signal (FR) of the first frequency divider (11). The phase difference of the output signal (FO) of the digitally controlled oscillator (19) relative to the output signal (FO) of the digitally controlled oscillator (19) is less than one cycle of the digitally controlled oscillator (19) and the digitally controlled oscillator (19) A first phase difference detection circuit (13) for measuring with a time resolution shorter than one cycle of the output signal (FO);
An output signal (FD) of the third frequency divider (12) and an output signal (FO) of the digitally controlled oscillator (19) are input, and an output signal (FD) of the third frequency divider (12). The phase difference of the output signal of the digitally controlled oscillator (FO) with respect to the output signal (FO) of the digitally controlled oscillator (19) is less than one cycle and the output signal of the digitally controlled oscillator (19) ( FO) a second phase difference detection circuit (14) for measuring with a time resolution shorter than one period,
The output signals (FR, FD) of the first frequency divider (11) and the third frequency divider (12) are inputted, and the output signal (FR) of the first frequency divider (11) is inputted. A determination unit (156) that determines whether the phase of the output signal (FD) of the third frequency divider (12) is advanced or delayed and outputs a determination result (SEL);
Of the output signal (RF) of the first frequency divider and the output signal (FD) of the third frequency divider, the edge of one output signal whose phase is advanced and the other output whose phase is delayed A counter (17) for providing a count value for the output signal (FO) of the digitally controlled oscillator (19) in a time period defined by a signal edge;
The count value of the counter (17), the outputs of the first and second phase difference detection circuits (13, 14), and the determination result of the determiner (15) are input, and the first frequency division A phase error calculator (16) for calculating a phase error (PERR) between the output signal (FR) of the detector (11) and the output signal (FD) of the third frequency divider (12);
A digital filter (18) that inputs the phase error (PERR) calculated by the phase error calculator (16) and outputs a filtered digital signal to the digital control oscillator (19). .

  The present invention includes a third phase difference detection circuit (21) that measures one period of the output signal (FO) of the digitally controlled oscillator (19), and the phase error calculator (16) includes the third phase difference calculator (16). The output signal (TRO) of the phase difference detection circuit (21) is input, and the measurement result of the phase difference in the first and second phase difference detection circuits (13, 14) is input to the third phase difference detection circuit. It is good also as a structure normalized by 1 period of the output signal (FO) of the said digital control oscillator (19) measured by (21).

  According to the present invention, it is possible to set the frequency division value of the post-stage frequency divider that divides the output of the DCO without extending the measurement range of the phase difference at the TDC.

It is a figure which shows the structure of one Embodiment of this invention. It is a figure explaining the phase calculation in one Embodiment of this invention. It is a figure which shows the structure of another embodiment of this invention. It is a figure explaining the counter in one Example of this invention. It is a figure explaining the error at the time of sampling. It is a figure explaining the example of sampling in one Example of this invention. It is a figure explaining the example of sampling in one Example of this invention. It is a figure explaining the case where the counter of FIG. 4 is an ideal counter. It is a figure explaining the case where the counter of FIG. 4 is a finite counter. It is a figure which shows the phase error detection characteristic in the case of an ideal counter. It is a figure which shows the phase error detection characteristic in the case of a finite counter. It is a figure which shows the phase error detection characteristic by the rewinding in the case of a finite counter. It is a figure which shows the phase error detection characteristic by one Example of this invention. It is a figure which shows an example of the typical structure of the analog PLL for multiplication. It is a figure which shows an example of the typical structure of analog PLL for Deskew. It is a figure which shows the usage example of analog PLL for Deskew. It is a figure which shows the structure of ADPLL of patent document 1 (Unexamined-Japanese-Patent No. 2002-076886). It is a figure which shows the structure of FIG. 17 typically. (A), (B) is a figure explaining the operation | movement of FIG. It is a figure which shows the phase comparison characteristic of ADPLL of patent document 1 (Unexamined-Japanese-Patent No. 2002-076886). It is a figure which shows the structure of ADPLL of patent document 2. FIG. It is a figure which shows the structure which converted ADPLL of patent document 1 (Unexamined-Japanese-Patent No. 2002-076886) into De-skew. It is a figure which shows the phase comparison characteristic in the structure of FIG. It is a figure which shows the structure of TDC of FIG. It is a figure which shows the timing operation | movement of TDC of FIG. It is a figure which shows the structure of TDC13 and 14 of FIG. It is a figure which shows the structure of TDC21 of FIG. It is a figure which shows the timing operation | movement of TDC of FIG.

  A preferred embodiment of the present invention will be described. FIG. 1 is a diagram showing an embodiment forming one of the preferred aspects of the present invention. Referring to FIG. 1, the digital PLL 10 receives a reference clock signal FREF from a terminal FREF and divides it by M, and a frequency divider (MDIV) 11 and a feedback clock signal FBAK from a terminal FBAK and divides it by N. A feedback frequency divider (NDIV) 12, a first TDC (Time-to-Digital-Converter) 13, a second TDC 14, a flip-flop (FF) 15, a phase error calculator (PERR) 16, , A counter (CONT) 17, a digital filter (DFIL) 18, a digitally controlled oscillator (DCO) 19, and a post-stage divider (PDIV) 20 that divides the output clock signal FO of the DCO 19 by P. The output clock signal FO of the DCO 19 is input to the counter 17 and the first and second TDCs 13 and 14. Although not particularly limited, in the following, a terminal to which a signal is input or output is designated by the same terminal name as the signal name.

  The digital PLL 10 in FIG. 1 operates so that the phase of the output signal FR of the pre-stage divider (MDIV) 11 and the output clock signal FO of the DCO 19 match, but further includes a second TDC 14 and a feedback frequency divider. The phase difference between the output signal FD of the device (NDIV) 12 and the output clock signal FO of the DCO 19 is also measured.

  In the embodiment of the present invention, when used as the De-skew PLL 30 as shown in FIG. 16, the output signal FOUT of the post-stage divider (PDIV) 20 is passed through the CTS 41 outside the PLL (see FIG. 16). Are fed back to the terminal FBAK. That is, in FIG. 1, a CTS (not shown) is inserted between the output terminal FOUT of the post-stage divider (PDIV) 20 and the input terminal FBAK of the feedback divider (NDIV) 12 as shown in FIG. The Although not particularly limited, in the following, in the TDC, counter, etc., the rising edge of the signal is defined as an effective edge. The first and second TDCs 13 and 14 measure the phase difference of the rising edge of the input signal, and the flip-flop (FF) 15 samples the signal of the data terminal at the rising edge of the signal input to the clock terminal, The counter 17 counts up at the rising edge of the FO when the count is enabled.

  The first TDC 13 inputs the output clock signal FO of the DCO 19 and the signal FR obtained by frequency-dividing the reference clock signal FREF by the previous stage frequency divider (MDIV) 11 to terminals A and B, respectively, and the rising edge of the FO The phase difference information TRO in which the phase difference (delay) of the rising edge of FR is converted into the delay element unit in the first TDC 13 is output. In other words, the rising edge of FO is equivalent to the number of delay elements of the delay element of the first TDC 13 than the rising edge of FR, or a value obtained by converting the number of delay element stages into FO1 period units is output as TRO.

  The second TDC 14 inputs the output clock signal FO of the DCO 19 and the signal FD obtained by dividing the feedback clock signal FBAK by N by the feedback frequency divider (NDIV) 12 to the terminals A and B. The rising edge of the FO and the FD A value obtained by converting the phase difference of the rising edge in units of delay elements in the second TDC 14 is output as phase difference information TDO. That is, the number of delay elements of the second TDC 14 equal to the delay of the second TDC 14 than the rising edge of the FR, or a value obtained by converting the number of delay element stages in units of one FO period is output as TRO. The first and second TDCs 13 and 14 may have the same configuration with respect to delay measurement range (number of delay element stages), accuracy (delay time of one delay element), and the like.

  The FF 15 inputs the frequency-divided signal FD of the feedback frequency divider (NDIV) 12 to the data terminal (D), inputs the output signal FR of the previous-stage frequency divider (MDIV) 11 to the clock terminal, and outputs FD at the rising edge of FR. Is output from the output terminal Q as an output signal SEL. SEL is Low if the phase of the rising edge of the FD is delayed with respect to the rising edge of the FR, and is High if the phase of the rising edge of the FD is advanced with respect to the rising edge of the FR. Note that the FD and FR input to the data terminal and the clock terminal of the FF 15 may be interchanged. In this case, the logic of the output signal SEL of the FF 15 with respect to the advance and delay of the phases of FR and FD is inverted, but this can be dealt with by considering the logic inverted by the counter 17 and the phase error calculator 16.

  The counter 17 uses one of FR and FD as a start signal and the other as an end signal in accordance with the output signal SEL of the FF 15, and counts the output clock FO of the DCO 19 during that time. For example, when the output signal SEL of the FF 15 is Low (logic 0), since the phase of the rising edge of the FD is delayed with respect to the rising edge of the FR, the counter 17 uses the signal FR (the rising edge) as a start signal. The signal FD (rising edge thereof) is used as an end signal, and the number of rising edges of the FO in the time period between the start signal and the end signal is counted.

  When the output signal SEL of the FF 15 is High (logic 1), since the phase of the rising edge of FR is delayed with respect to the rising edge of FD, the counter 17 uses FD (rising edge) as a start signal, and FR ( Is used as the end signal, and the number of rising edges of the FO in the time period between the start signal and the end signal is counted.

  The counter 17 obtains an integer part of the phase difference between FR and FD (the number of rising edges of the FO), and the first and second TDCs 13 and 14 use (FO-FR) and (FO- The phase difference of the fractional part of FD) is measured with the precision of decimals (one TDC delay element) within one period of FO.

From (FO-FR) (= TRO) and (FO-FD) (= TDO) measured by the first and second TDCs 13 and 14, for example, TRO-TDO = (FO-FR)-(FO- FD) = FD-FR (7)
Thus, the decimal part of the phase difference between FR and FD (delay value less than one FO period) is obtained as the number of delay element stages of TDC.

  The output signals TRO and TDO (decimal values) of the first and second TDCs 13 and 14, the output signal SEL of the FF 15, and the count value (integer value) of the counter 17 are input to the phase error calculator 16.

  The phase error calculator 16 calculates the phase error of the FR and FD phase error PERR from the difference between the count value (integer value) of the counter 17 and TRO and TDO. When the rising edge of FR is temporally advanced from the rising edge of FD (SEL = Low), the phase error PERR can be obtained, for example, by the following equation (8).

  PERR = count value−TRO + TDO (8)

  When the rising edge of the FD is ahead of the rising edge of the FR (SEL = High), the phase error PERR can be obtained by the following equation (9), for example.

  PERR = count value−TDO + TRO (9)

  The digital filter 18 is configured as a low-pass filter (FIR (Finite Impulse Response Filter)) that smoothes the phase difference PERR, and outputs a digital signal DCODE that is a filter calculation result.

  The DCO 19 varies the LC resonance frequency by varying the capacitances of the plurality of varactor diodes based on the logic 1 and 0 signals based on the digital signal DCODE.

  As the first and second TDCs 13 and 14 in FIG. 1, a basic TDC as shown in FIG. 26 can be used. The configuration shown in FIG. 26 is basically the same as the configuration of the TDC shown in FIG.

  In FIG. 26, the TDC measures the phase difference between the rising edges of the signals input to the terminals A and B, respectively. The signal input to the terminal A is delayed by a delay element array composed of a plurality of stages of unit delay elements (buffers) 211. The signal of each stage of the delay element array is input to the data terminal of the FF 212 provided corresponding to each stage, and the signal input to the terminal B is input to the clock terminals of the plurality of FFs 212 in common. In each FF 212, the signal at the data terminal is sampled at the rising edge of the signal input in common to the clock terminal. An AND circuit 213 is provided for inputting a signal obtained by inverting the output of each FF 212 and the output of the adjacent (following) FF 212 by an inverter 214. The AND circuit 213 outputs “1” when the output of the FF 212 is “1”, the output of the adjacent (following) FF 212 is “0”, and therefore the output of the inverter 214 is “1”, otherwise “0”. (The AND circuit 213 constitutes the edge detection circuit of FIG. 24, and outputs an FF in which the output of the previous FF is 1 and the output of the FF is 0 among the samples of the plurality of FFs 212. To detect). The outputs of the plurality of AND circuits 213 are converted into parallel bits and decoded by a binary decoder 215. The output OUT of the binarization decoder 215 outputs the number of stages of the buffer 211 corresponding to the phase difference of the rising edges of the signals input to the terminals A and B as digital data.

  As an example of the operation in FIG. 26, for example, when a signal input to the terminal B rises after a delay time such as a phase separation of one stage of the buffer from the rising edge of the signal input to the terminal A, Although the signal (High level) input to the terminal A has already propagated for one stage of the buffer at the rise of the signal commonly input to the clock terminal, the output of the first stage buffer 211 is “1”. The outputs of the buffers 211 in the second and subsequent stages are all “0”. Therefore, the output of the AND circuit 213 which receives the output 1 of the first stage FF 212 and the output 0 of the second stage FF 212 is “1”, and the outputs of all the remaining AND circuits 213 are “0”. It can be seen that the phase difference between the A and B signals corresponds to a delay of one buffer stage. 26, by delaying the signal input to the terminal A by the delay element array, the phase of the rising edge of the signal input to the terminal A is more than that of the rising edge of the signal input to the terminal B. When the phase difference between the two signals in the case of advance is detected, but the rising edge of the signal input to the terminal A is delayed in time from the rising edge of the signal input to the terminal B The phase difference between the rising edge of the signal input to the terminal A one cycle (cycle) before the rising edge of the signal input to the terminal B is detected, and the phase difference is detected from one period of the signal input to the terminal A. The value obtained by subtracting is the phase delay of the signal input to the terminal A.

  Needless to say, the first and second TDCs 13 and 14 may use TDC_RISE as an output signal in the TDC shown in FIG.

  Next, the operation principle of the embodiment shown in FIG. 1 will be described with reference to FIG. As shown in FIG. 2, in this embodiment, the phase difference between the rising edges of FO and FR and the phase difference between the rising edges of FO and FD are measured by the first and second TDCs 13 and 14, respectively. The phase difference between FR and FD is measured.

  In the example shown in FIG. 2, since the phase of the rising edge of FD is delayed with respect to the rising edge of FR, the counter 17 sets the rising edge of the high pulse of FR to a count start signal (for example, count enable (permit) )), And the rising edge of the high pulse of FD is used as a count end signal (set to count disable (not permitted)), and the number of rising edges of FO in the meantime is counted. In the case of FIG. 2, the number of rising edges of the FO counted by the counter 17 is “3”.

In the first TDC 13, the phase of the rising edge of the FO input to the terminal A is ahead of the phase of the rising edge of the FR input to the terminal B. In the first TDC 13, the phase difference between FO and FR is TRO. = FO-FR = 0.2
Is measured. Note that TRO = 0.2 is the result of converting the number of unit delay element stages in the first TDC 13 into one FO cycle. For example, when one period of the FO is 10 in terms of the number of unit delay elements in the first TDC 13, the FO corresponds to the phase advancement of the unit delay element by two stages, etc., compared to the FR.

In the second TDC 14, the phase of the rising edge of the FO input to the terminal A is more advanced than that of the rising edge of the FD input to the terminal B. In the second TDC 14, the phase difference between the FO and the FD is obtained. ,
TDO = FO-FD = 0.4
(TDO = 0.4 is the result of converting the number of delay element stages in the second TDC 14 into one FO cycle).

  In the example of FIG. 2, the phase of the rising edge of FR is ahead of the phase of the rising edge of FD (rising to High first in time), the output SEL of FF 15 becomes 0, and the phase error calculator 16 From Equation (8), the phase difference PERR between FR and FD is obtained as follows.

PERR = count value−TRO + TDO
= 3-0.2 + 0.4
= 3.2

  In one embodiment of the present invention, the first and second TDCs 13 and 14 may correspond to the measurement time for one FO cycle. That is, it is not necessary to extend the measurement time in the first and second TDCs 13 and 14 regardless of the setting of the P division of the post-stage divider (PDIV) 20, and the rising edges of FR and FD It is possible to lock the PLL so that the phase difference becomes zero (the rising edge timings coincide). However, it is necessary to match the delays in the pre-stage frequency divider (MDIV) 11 and the feedback frequency divider (NDIV) 12. Note that this delay adjustment is also necessary for the pre-stage divider (MDIV) 31 and the feedback divider (NDIV) 32 in the analog PLL of FIG.

  In one embodiment of the present invention, the first TDC 13 that measures the phase difference between FO and FR with reference to the rising edge of FR, and the second that measures the phase difference between FO and FD with reference to the rising edge of FD. The TDC 14 is provided, and the measurement range of the phase difference in each of the first and second TDCs 13 and 14 may be one FO period.

  In one embodiment of the present invention, as in the related art described above, in the TDC, it is unnecessary to measure the length of P periods of the FO (division value P is, for example, 16). An increase in the number of circuits is suppressed, and an area-saving De-Skew ADPLL configuration is possible.

  In one embodiment of the present invention, the phase difference (decimal part) measured by TDC is used in one period of FO, and the integer part is counted in one period of FO. The correspondence (phase comparison characteristic) between the phase difference between FR and FD) and the output digital code of the phase error calculator 16 is the same as in FIG. However, when the configuration of FIG. 1 is realized as an actual circuit, there are some points to be improved. In the following, some improvements will be described as examples.

<TDC replica>
First, an embodiment in which a TDC replica is added to the configuration of FIG. 1 will be described. When performing normalization processing of the measurement results in the TDC, that is, processing for converting the phase difference of the stage number information of the delay elements into a ratio to the period of the output signal FO1 of the DCO, the number of stages of the delay elements in the TDC equivalent to the FO1 period is calculated. It is necessary to measure. In one embodiment of the present invention, a TDC that measures one FO cycle is prepared separately.

  FIG. 3 is a diagram showing the configuration of this embodiment. In FIG. 3, the same reference numerals are assigned to elements that are the same as or equivalent to the configuration of the embodiment shown in FIG. Hereinafter, the description of the same or equivalent elements is omitted.

  In FIG. 3, the TDC replica 21 added to the embodiment of FIG. 1 receives the output clock signal FO of the DCO 19 and inputs the measurement result TREP of the FO1 period (a value obtained by converting the FO1 period into the number of delay element stages of the TDC). Output. In the phase error calculator 16, for example, the outputs of the first and second TDCs 13 and 14 (represented by the number of stages of delay elements) are used as TREP from the TDC replica 21 (the number of delay stages such as one period phase of FO). Normalized to a decimal number between 0 and 1.

  The TDC replica 21 of FIG. 3 has the same number of delay element stages as the FO1 period by inputting the FO in common to the A terminal and the B terminal in the TDC of FIG. 26 described as the configuration example of the TDCs 13 and 14 of FIG. Can be measured. Alternatively, when the duty of the FO is 50%, the pulse width of the high pulse may be obtained from the TDC output TDC_FALL and TDC_RISE of FIG. 24, and one cycle may be obtained by doubling the pulse width.

  FIG. 27 shows another example of the configuration of the TDC replica 21. The basic configuration of FIG. 27 is the same as that of FIG. 26, but includes a moving average circuit that performs moving average (smoothing) the measurement result of one period of the FO, and outputs the result of moving average as the FO period signal TREP. Referring to FIG. 27, similarly to FIG. 26, m + 1 flip-flops (FF1 to FFm + 1), m + 1 delay elements (BO1, BO2,... BOm + 1), and each flip-flop (FF1 to FFm) The AND circuit (AND1 to ANDm) that takes the AND of the inverted signals of the flip-flops (FF2 to FFm + 1) on the right and the outputs FOW [m-1] to FOW [0] of the AND circuit (AND1 to ANDm) are buses The binarized encoder 301 that receives the converted m-bit signal FOW [m−1: 0] and the moving average circuit 302 that takes the moving average of the output FOW_BIN of the binarized encoder 301 and outputs the result as TREP are provided.

  FIG. 28 is a timing chart showing an example of the operation of the TDC replica 21 of FIG. One period of FO is detected as the number of stages of delay elements, and based on the value, an FO period signal TREP is generated. The delay from the rising edge of the FO to the rising edge of the next cycle is measured. At time t1, FO rises to High, delays from FO at time t2, and FO1 rises to High. Similarly, FO2 to FOm rise to High with a predetermined delay from the output of the previous stage, and FOm + 1 becomes High at time t3. Stand up to. High level delay clocks FOk to FOm-1 (0 <k <m-1) are input to the data terminals of the flip-flops FFk to FFm-1 with respect to the rising edge of the FO, and the outputs of the flip-flops FFk to FFm-1 Sampling signals FOPk to FOPm-1 rise to High at time t1. Since the sampling signal FOPm is Low, the output of the AND circuit ANDm-1 becomes “1”, and only the edge extraction signal FOW [1] becomes High at time t1. In the other AND circuits, since either one of the input terminals is 0, the output is Low. The binarizing encoder 301 outputs digital data FOW_BIN in response to the edge detection signal FOW [m−1: 0]. In the case of the example of FIG. 28, FOW_BIN is output as “m−1” as digital data FOW_BIN, assuming that (m-FOW_BIN) stages of delay elements correspond to one cycle of the output clock FO of the DCO 19. A predetermined number of FOW_BINs are averaged (smoothed) by the moving average circuit 302 that inputs the FO as a clock, and the averaged value is output as the FO cycle signal TREP. According to such a configuration, even if the value of FOW_BIN is shifted due to jitter, noise, or the like of the output signal FO of the DCO 19, it is absorbed by averaging the shift, and more accurate measurement of one cycle of the clock FO is possible. Is possible.

<Counter configuration>
Next, a counter change and synchronous / asynchronous processing will be described as another embodiment of the present invention. In an actual circuit (real circuit), when the PLL is locked, the rising edge of FR and the rising edge of FD are almost in the vicinity.

  In the embodiment of FIG. 1, the FF 15 determines the delay and advance of FR and FD, and the start / end of the counter 17 is controlled by FR / FD. Which signal of FR / FD is used to start / stop the counting operation of the FO in the counter 17 is selected by the output SEL of the FF 15, and if the rising edge of the FR is ahead of the rising edge of the FD, Control is performed so that FR starts the counter 17 and FD ends. This control is difficult to realize when the edges of FR and FD (rising edges) are in the vicinity. Also, the counter 17 itself takes only 0 or 1 in the vicinity of the lock (in the lock state, the count value corresponding to the integer part of the phase difference between FD and FR swings around 0 or 1). For this reason, reset release and high-speed count operation are required. However, since it is considered that the realization is quite difficult, it is not a configuration in which FR / FD is used as a control signal for controlling the start / end of the counter 17, but as shown in FIG. The counter value of (CONT) 17 may be sampled by FR and FD.

  In other words, in FIG. 4, the counter 17 always counts FO, samples (latches) the count value at the rising edge of each pulse of FR and FD, and count values sampled at two points before and after in time. From the difference, the phase difference between FR and FD (the integer part, how many FO edges are present) is obtained. The counter 17 changes the count value at the timing of the rising edge of the FO, for example, and samples (latches) the count value of the counter 17 at the rising edge of the FR or FD that is asynchronous with the FO. Therefore, since FO, FR, and FD are asynchronous (edges are close to each other but not in a synchronous relationship), the sampling timing of FR and FD may overlap with the timing at which the count value of FO transitions. .

  For example, as illustrated in FIG. 5, when the count value changes (Tdx in FIG. 5) and the sampling timing of the count value by FR / FD overlap (timing at the position indicated by X in FIG. 5), correct data is obtained. It cannot be imported. Tdata is one data period in the counter 17 and corresponds to one cycle of FO.

In order to avoid this problem, FR and FD are
Tdx <Tdsa <2 × Tdsa <Tdata (10)
Signals delayed by a delay time Tdsa that satisfies 2 × Tdsa are generated, the count value of the counter 17 is sampled with these delay signals, and the correct value is determined from the sampled values.

  In the example shown in FIG. 6, delayed signals FR1 and FR2 obtained by delaying FR by Tdsa and 2 × Tdsa are created, and the count value of the counter 17 is sampled at each rising edge of the three signals FR, FR1 and FR3. Although the sample value by FR is X (NG), B is taken in by FR1 and FR2, and determination is made together with the state (phase difference) at TDC. In this case, B is used as the count value sampled by FR.

  In the example of FIG. 6, the count value of the counter 17 of FIG. 4 is binary data (binary counter). In the case of binary data, when a carry occurs, the transition time is long and the possibility of sampling error data is increased. This concern is eliminated by changing the binary counter to a Gray code counter.

  In Gray code, when changing from one value to an adjacent value, only one bit shift always changes. In FIG. 6, even if the portion of the count value X is sampled, the count value before or after that can be captured (captured). For this reason, two sampling points are sufficient.

  In FIG. 7, when FR is A and when FR1 is delayed by Tdsa from FR, when B is sampled, the state of TDC 13 (FO and FR phase advance / delay) is also determined (determined by phase error calculation circuit 16). ). In this case, B is used.

  As the counter 17 for counting FO, a gray code counter is used, and as shown in FIG. 4, in the configuration in which the count value of the counter 17 that is always operating is sampled as FO with FR and FD, the counter 17 always keeps moving. When counting up to the full bit of the counter, auto-clearing is performed and counting up is started again from 0. When the timing of sampling of FR and FD sandwiches auto-clear, the phase error of the integer part (integer part) measured by the counter 17 may be an incorrect value.

  That is, as shown in FIG. 8, in the case of an ideal counter with an infinite counter value, the integer part of the phase difference between FR and FD can be detected by the difference between the values obtained by sampling the count value of the counter 17 by FR and FD. Is possible.

Integer part of phase error = FD counter value−FR counter value (11)
(However, if the phase error is positive, it corresponds to delay, and if it is negative, it corresponds to advance.)

In the case of (1) in FIG.
FD counter value (= 258) −FR counter value (= 6)
= 258-6
= 252 (Delayed)

In the case of (2) in FIG.
FD counter value (= 250) −FR counter value (= 578)
= 250-578
= -328 (advance)

However, when the counter value is finite (for example, 8 bits: 0 to 255), as shown in FIG.
In case of (1)
The counter value of FD = 258 is
258 modulo 256 = 2 (258-256 = 2)
And
FD counter value (= 2) -FR counter value (= 6)
= 2-6
= -4 (advance)
It becomes.

In the case of (2), 578 is
578 modulo 256 = 66
And
FD counter value (= 250) −FR counter value (= 578)
= 250-66
= 184 (Delayed)
It becomes.

  FIG. 10 shows the phase error detection characteristics when an ideal counter (infinite counter) is used as the counter 17. The horizontal axis represents the phase difference (phase difference between FR and FD), and the vertical axis represents the phase error counter value (count value of the counter 17). As the phase difference becomes larger or smaller (negatively larger), the phase error counter value also becomes larger or smaller (negatively larger) and has a constant gradient.

  FIG. 11 shows the phase error detection characteristics when a finite counter is used as the counter 17 of FIG. In the case of a finite counter, the phase difference that can be measured is theoretically up to the maximum value ± Max of the counter. Further, in the following, it rewinds to 0 again.

  The solid line in FIG. 12 is the same as the characteristic in FIG. 11, but the characteristic indicated by the broken line may be traced depending on the state. In this case, when calculating the phase difference between FR and FD, the counter 17 is rewound to 0 between the count values of the edges to be compared between the FR and FD edges.

FD counter value−FR counter value = 258−6
= 252
The counter should be 0 between the FR and FD edges,
FD counter value−FR counter value = 2-6
= -4
Is mapped.

  In this case, both the original phase difference and the delay / advance information can take erroneous information. Therefore, in this embodiment, not only the determination of the phase difference ± of FR and FD, but also the determination of the delay / advance of the phase of FR and FD using the output signal SEL of FF 15 in FIG. Remaps the state that should be a positive value, a negative value, a negative value, and a positive value. FR / FD phase lag / advance due to SEL signal (logic rising 1 when FD rising edge is ahead of FR rising edge (when phase difference is +), logic 1 when lagging) As shown in FIG. 13, when the polarity of the phase error counter value is different, the value of the SEL signal is reflected in the phase error counter value. When the sign of the phase error (phase error counter value) is equal to the SEL signal, the phase error (phase error counter value) is output as it is, and when the sign bit of the phase error (phase error counter value) is different from the SEL signal, the SEL signal Match the sign bit to.

  Alternatively, if the sign of the phase error counter value is different from the polarity of the Bang-Bang characteristic (a characteristic in which the phase difference is a positive value in the region where the phase difference is + and a negative value in the region where the phase difference is a negative value), the mapping is further restored. .

FD counter value−FR counter value = 2-6
= -4
in the case of,
Because the polarity of the Bang-Bang characteristic is positive,
-4 + 256 = 252
Map back to the original.

  As a result, the characteristic indicated by the broken line in FIG. 13 becomes the original characteristic indicated by the solid line. In the example illustrated in FIG. 13, the counter takes values from −255 (binary representation: 00000001) to −1 (binary representation: 11111111) and 0 to +255 (binary representation: 11111111).

  The embodiment with the above improvements becomes a circuit configuration that can be finally implemented (implemented), and can be realized as an ADPLL for De-Skew.

  According to the present embodiment, a multiplication PLL (SSCG (Spread Spectrum Clock Generator)) as well as a De-skew ADPLL can be configured.

  As described above, according to the present embodiment, since the TDCs 13 and 14 are provided (that is, by adding one TDC 14), each phase difference is measured through the FO, Since the configuration is such that the FR-FD phase difference to be finally obtained by calculation is obtained, the ADPLL for De-Skew can be configured without increasing the TDC phase difference measurement time.

  In the above embodiment, the phase difference between the rising edges of FO and FR and FO and FD has been described as an example in TDCs 13 and 14, but the signal edge is not limited to the rising edge, and the falling edge is It is good also as a structure to use.

  The disclosures of Patent Documents 1 and 2 and Non-Patent Document 1 are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 TDC
2 FF
3 Accumulator 4 Accumulator 5 Normalization circuit (DCO period normalization)
6 Phase detector 8 Sampler 10, 30 ADPLL
11, 31 Pre-stage divider 12, 32 Feedback divider 13 TDC
14 TDC
15 FF
16 Phase error calculator 17 Counter 18 Digital filter 19 Digitally controlled oscillator 20, 37 Post-stage divider 21 TDC replica 33 Phase frequency comparator 34 Charge pump 35 Analog filter 36 Voltage controlled oscillator 41, 42 CTS
43, 44 User logic 102 Accumulator 106 Waveform shaper 110 FREF
112 CKR
118 Incrementer 120 Latch 116 FCW
201 TDC
211 Buffer (delay element)
212 Flip-flop 213 AND circuit 214 Inverter 215 Binary decoder 301 Binary encoder 302 Moving average circuit 401 Delay Line
402 Control Logic
403 Sampler
405 Adder 404 Counter
406 Offset Control
407 Prescaler
408 Program Counter
409 Swallow Counter

Claims (14)

The third clock signal is effective during the time period between the clock signal whose phase is advanced and the clock signal whose phase is delayed among the input first clock signal and second clock signal. A counter that counts how many edges there are;
A first phase difference detection circuit for measuring a phase difference between the first clock signal and the third clock signal with a time resolution shorter than one cycle of the third clock signal;
A second phase difference detection circuit for measuring a phase difference between the second clock signal and the third clock signal with a time resolution shorter than one cycle of the third clock signal;
A determinator for determining which of the first clock signal and the second clock signal is advanced in phase;
A phase for calculating a phase error between the first clock signal and the second clock signal based on the output of the counter, the outputs of the first and second phase difference detection circuits, and the output of the determiner. An error calculator;
A digital filter for smoothing the phase error;
A digitally controlled oscillator that varies the oscillation frequency based on the phase error smoothed by the digital filter and outputs the third clock signal;
With
2. The digital phase-locked loop circuit according to claim 1, wherein the second clock signal is generated from a signal obtained by dividing the third clock signal. A first frequency divider for receiving and dividing a reference clock signal and outputting the first clock signal;
A second frequency divider that receives and divides the third clock signal and outputs an output clock signal;
A third frequency divider that receives and divides a signal obtained by feeding back the output clock signal of the second frequency divider and outputs the second clock signal;
With
The first phase difference detection circuit includes:
The first clock signal output from the first frequency divider and the third clock signal are input, and a level between effective edges of the first clock signal and the third clock signal is input. Measuring the phase difference with a time resolution shorter than one period of the third clock signal and within a measurement range of one period or less of the third clock signal;
The second phase difference detection circuit includes:
The second clock signal output from the third frequency divider and the third clock signal are input, and a level between the second clock signal and an effective edge of the third clock signal is input. Measuring the phase difference with a time resolution shorter than one period of the third clock signal and within a measurement range of one period or less of the third clock signal;
The determiner is
One of the first clock signal from the first divider and the second clock signal from the third divider is input to a clock terminal, the other is input to a data terminal, and the first A flip-flop that determines and outputs whether the phase of the effective edge of the second clock is advanced or delayed with respect to the effective edge of the clock signal;
The counter is
Of the first clock signal and the second clock signal, a valid edge of one clock signal whose phase is advanced and a valid time range of the other clock signal whose phase is delayed 2. The digital phase-locked loop circuit according to claim 1, wherein a count value of valid edges of the third clock signal is provided. A first frequency divider that inputs and divides a reference clock signal and outputs a first clock signal;
A digitally controlled oscillator that varies the oscillation frequency according to the input digital signal and outputs a third clock signal;
A second frequency divider that inputs and divides the third clock signal from the digitally controlled oscillator and outputs an output clock signal;
A third frequency divider that inputs and divides a signal obtained by feeding back the output clock signal output from the second frequency divider and outputs a second clock signal;
The first clock signal from the first frequency divider and the third clock signal from the digitally controlled oscillator are input, and a valid edge of the first clock signal and the third clock signal are input. The first phase difference detection circuit that measures the phase difference between the valid edges of the third clock signal with a time resolution shorter than one period of the third clock signal and within a measurement range of one period or less of the third clock signal. When,
The second clock signal from the third frequency divider and the third clock signal from the digitally controlled oscillator are input, and a valid edge of the second clock signal and the third clock signal are input. A second phase difference detection circuit for measuring a phase difference between the effective edges of the third clock signal with a time resolution shorter than one period of the third clock signal and within a measurement range of one period or less of the third clock signal. When,
One of the first clock signal from the first divider and the second clock signal from the third divider is input to a clock terminal, the other is input to a data terminal, and the first A determiner comprising a flip-flop that determines and outputs whether the phase of the effective edge of the second clock is advanced or delayed with respect to the effective edge of the clock signal;
Inputting the first clock signal from the first frequency divider, the second clock signal from the third frequency divider, and the third clock signal from the digitally controlled oscillator; Of the first clock signal and the second clock signal, the valid edge of one clock signal whose phase is advanced and the valid period of the other clock signal whose phase is delayed, within a time period defined by A counter providing a count value of valid edges of the third clock signal;
The count value of the counter, the outputs of the first and second phase difference detection circuits, and the determination result of the determiner are input, and the first clock signal and the second clock signal are validated. A phase error calculator for calculating the phase difference between edges;
A digital filter that inputs a phase difference calculated by the phase error calculator and outputs a filtered digital signal to the digitally controlled oscillator;
A digital phase-locked loop circuit comprising: The counter starts counting the third clock signal based on one of the first clock signal and the second clock signal, the phase of which precedes, based on the determination result of the determiner. ,
The counting operation of the third clock signal from the digitally controlled oscillator is stopped by the other clock signal having a phase lag among the first clock signal and the second clock signal. Item 4. The digital phase-locked loop circuit according to Item 3. The counter counts the third clock signal;
The count value of the counter is latched at an effective edge of one of the first clock signal and the second clock signal, the phase of which is advanced,
The count value of the counter is latched at the valid edge of the other clock signal whose phase is delayed among the first clock signal and the second clock signal,
The difference between the count value sampled at the edge of one clock signal whose phase is advanced and the count value sampled at the edge of the other clock signal whose phase is delayed is taken, and the phase is advanced by the difference. And the count value of the valid edge of the third clock signal within a time period defined by the edge of one clock signal that is delayed and the edge of the other clock signal that is delayed in phase. The digital phase-locked loop circuit according to claim 3. Generating at least one delayed signal obtained by delaying the clock signal by a predetermined time with respect to at least one of the first clock signal and the second clock signal;
6. The digital phase-locked loop circuit according to claim 5, wherein in the counter, the count value of the counter is sampled with the delay signal for at least one of the first clock signal and the second clock signal. .   The phase error computing unit is calculated from a plurality of count values obtained by sampling the count value of the counter using the clock signal and the delay signal, and a phase difference of the first phase difference detection circuit or the second phase difference detection circuit. 7. The digital phase-locked loop circuit according to claim 5, wherein one count value is selected.   8. The digital phase-locked loop circuit according to claim 5, wherein the counter is a counter that outputs a count value as a Gray code. 9. The counter always counts the third clock signal from the digitally controlled oscillator, and counts again from the count value 0 when the count value reaches the maximum value,
Based on the determination result of whether the phase of the second clock signal is advanced or delayed with respect to the first clock signal, the count value latched at the effective edge of one of the clock signals whose phase is advanced, Correcting the difference in response to a case where the counter value of the counter is rewound to 0 between the count value latched at the valid edge of the other clock signal whose phase is delayed, and The digital phase-locked loop circuit according to claim 5, wherein: A third phase difference detection circuit for measuring one period of the third clock signal from the digitally controlled oscillator;
The phase error calculator inputs an output signal of the third phase difference detection circuit, and the measurement result of the phase difference in the first and second phase difference detection circuits is received by the third phase difference detection circuit. 10. The digital phase-locked loop circuit according to claim 2, wherein the digital phase-locked loop circuit is normalized by one cycle of the third clock signal from the measured digitally controlled oscillator. The first and second phase difference detection circuits are respectively
Having first and second terminals;
A plurality of cascaded first delay elements for delaying a first signal input to the first terminal;
A first flip-flop that samples the first signal at a valid edge of a second signal input to the second terminal;
A plurality of second flip-flops that sample the outputs of the plurality of first delay elements at the edge of the second signal in common with the first flip-flops;
A first detection circuit for detecting whether or not the output of the first flip-flop and the output of the second flip-flop in the first stage are a combination of predetermined values;
A plurality of second detection circuits for detecting whether or not outputs of two adjacent flip-flops of the second and subsequent second flip-flops are a combination of predetermined values;
A circuit that receives detection results from the first detection circuit, the plurality of second detection circuits, and encodes the phase difference into a binary code;
The digital phase-locked loop circuit according to claim 1, further comprising: The third phase difference detection circuit has first and second terminals for commonly inputting the third clock signal from the digitally controlled oscillator,
A plurality of cascaded first delay elements for delaying a first signal input to the first terminal;
A first flip-flop that samples the first signal at a valid edge of a second signal input to the second terminal;
A plurality of second flip-flops that sample the outputs of the plurality of first delay elements at the edge of the second signal in common with the first flip-flops;
A first detection circuit for detecting whether or not the output of the first flip-flop and the output of the second flip-flop in the first stage are a combination of predetermined values;
A plurality of second detection circuits for detecting whether or not outputs of two adjacent flip-flops of the second and subsequent second flip-flops are a combination of predetermined values;
A circuit that receives detection results from the first detection circuit, the plurality of second detection circuits, and encodes the phase difference into a binary code;
A circuit that outputs a result obtained by taking a predetermined number moving average of the encoding results as one cycle;
The digital phase-locked loop circuit according to claim 10, comprising:   An output clock signal from the second frequency divider is input to a clock tree synthesis buffer in a feedback path, and an output of the clock tree synthesis buffer is input to the third frequency divider. The digital phase-locked loop circuit according to claim 1.   A semiconductor device comprising the digital phase-locked loop circuit according to claim 1.

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