JP2013058881A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that reconciles improved C/N and fast frequency switching.SOLUTION: The present invention relates to a PLL circuit P including: a DCO 1 for outputting an output signal CKV such that a phase difference of the output signal CKV from a reference signal FREF is zero; a phase detector 10 for outputting a digital signal indicating the phase difference; an EXOR phase comparator 21 for outputting an analog signal indicating the phase difference, with a linear characteristic between the phase difference and the analog signal in a range of phase difference corresponding to at least one least significant bit of the digital signal and including a phase difference of zero; and a switching control section S for switching the entity of phase comparison from the phase detector 10 to the EXOR phase comparator 21 when the phase difference indicated by the digital signal enters the range of phase difference corresponding to one least significant bit of the digital signal and including a phase difference of zero.

Description

  The present invention relates to a PLL (Phase-Locked Loop) circuit that outputs a signal having a desired frequency based on a reference signal.

  A PLL circuit is used in a frequency synthesizer or a clock generation circuit of a wireless communication circuit. In recent years, an all-digital PLL (ADPLL) circuit that can operate at a low power supply voltage and can reduce the chip size has been studied (see, for example, Non-Patent Document 1).

  The ADPLL circuit includes a digitally controlled oscillator (DCO) and a digital phase comparator as an alternative to the voltage controlled oscillator (VCO) and analog phase comparator of the analog PLL circuit.

“ALL-DIGITAL FREQUENCY SYNTHEZSIZER in DEEP-SUBMICRON CMOS” Robert Bogdan Stanzewski / Poras T. By Balsara

  Since the digital phase comparator has a step characteristic between the phase difference and the digital signal, the digital phase comparator generates an uncontrolled fluctuation with respect to the control voltage of the DCO and degrades the C / N. Here, if the number of bits of the digital signal is increased, the digital phase comparator can reduce, but cannot eliminate, uncontrolled fluctuations with respect to the control voltage of the DCO.

  Since the analog phase comparator (particularly EXOR type) has a linear characteristic between the phase difference and the analog signal, it does not generate uncontrolled fluctuations with respect to the control voltage of the VCO, and improves C / N. However, analog phase comparators cannot switch frequencies at high speed.

  Accordingly, in order to solve the above-described problems, an object of the present invention is to provide a PLL circuit that achieves both improvement of C / N and high-speed frequency switching.

  In order to achieve the above object, when starting the lock operation, a digital phase comparator is used to realize high-speed frequency switching, and after the lock operation is completed, the analog phase comparator is turned on. By using it, it was decided to improve C / N.

  Specifically, the present invention includes an oscillation unit that outputs the output signal such that the phase difference between the reference signal and the output signal is 0, and a digital phase comparison unit that outputs a digital signal indicating the phase difference. Output an analog signal indicating the phase difference, and correspond to at least one least significant bit of the digital signal and include a phase difference between the phase difference and the analog signal within a range of the phase difference including 0 as the phase difference. An analog phase comparison unit having characteristics, and when the phase difference indicated by the digital signal falls within a range of the phase difference corresponding to the least significant 1 bit of the digital signal and including 0 as the phase difference A switching control unit that switches the main body from the digital phase comparison unit to the analog phase comparison unit.

  According to this configuration, it is possible to provide a PLL circuit that achieves both improvement in C / N and high-speed frequency switching in the initial lock operation.

  Further, in the present invention, the analog phase comparison unit has a linear characteristic between the phase difference and the analog signal within a range of the phase difference corresponding to the least significant 1 bit of the digital signal. When the phase difference indicated by the signal falls outside the range of the phase difference corresponding to the least significant 1 bit of the digital signal and including 0 as the phase difference, the switching control unit sets the main subject of the phase comparison as the analog The PLL circuit is characterized by switching from a phase comparator to the digital phase comparator.

  According to this configuration, it is possible to provide a PLL circuit that achieves both improvement of C / N and high-speed frequency switching in the locking operation from unlocking.

  In the present invention, the analog phase comparator has a linear characteristic between the phase difference and the analog signal within a range of the phase difference corresponding to the lower m bits (m> 1) of the digital signal. When the phase difference indicated by the analog signal corresponds to the lower n bits (m> n> 1) of the digital signal and falls outside the range of the phase difference including 0 as the phase difference, the switching control is performed. The unit is a PLL circuit that switches the subject of phase comparison from the analog phase comparison unit to the digital phase comparison unit.

  According to this configuration, in the locking operation from unlocking, in addition to achieving both C / N improvement and high-speed frequency switching, it recognizes in which direction the phase difference deviates from the above range. A PLL circuit can be provided.

  The present invention can provide a PLL circuit that achieves both improvement in C / N and high-speed frequency switching.

It is a figure which shows the structure of the PLL circuit of this invention. It is a figure which shows a digital phase detection characteristic. It is a figure which shows an analog phase detection characteristic. It is a figure which shows the process of the first locking operation. It is a figure which shows the process of the lock operation | movement from unlocking. It is a figure which shows an analog phase detection characteristic. It is a figure which shows the process of the lock operation | movement from unlocking.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments.

(Outline of PLL circuit)
The configuration of the PLL circuit of the present invention is shown in FIG. The PLL circuit P includes a digital PLL circuit D, an analog PLL circuit A, a switching control unit S, and a two-frequency divider F. When the PLL circuit P starts the first locking operation, the switching control unit S uses the digital phase comparator of the digital PLL circuit D, while the switching operation is performed after the PLL circuit P finishes the first locking operation. The control unit S uses the analog phase comparator of the analog PLL circuit A. When the PLL circuit P starts the locking operation from unlocking, the switching control unit S uses the digital phase comparator of the digital PLL circuit D, while the PLL circuit P completes the locking operation from unlocking. Later, the switching control unit S uses the analog phase comparator of the analog PLL circuit A.

  The digital PLL circuit D includes a DCO 1, D / A (Digital-Analog Converter) 2, LPF (Low Pass Filter) 3, TDC 4, sampler 5, reference phase accumulator 6, multiplier 7, variable phase accumulator 8, sampler 9, phase It comprises a detector 10, a loop filter 11 and a gain normalization circuit 12.

  The DCO 1 has a varactor (variable capacitance diode) array and can control the oscillation frequency with a binary code. Here, when the oscillation frequency of the DCO 1 is a wide band and the switching frequency interval is small, the number of bits of the varactor may become so large that it cannot be realized. Thus, a feasible varactor array can be configured by a method (discrete tuning) that reduces the frequency range in a stepwise manner and improves the frequency resolution.

  For example, there is a varactor array having a plurality of banks into which binary code is input. The first bank can be locked at a frequency range of 2316 kHz with a variable range of 400 MHz, the second bank can be locked at a frequency interval of 461 kHz with a variable range of 118 MHz, and the third bank can be locked at a frequency range of 23 MHz with a variable range of 1.5 MHz. Can be locked at frequency intervals. The first bank, the second bank, and the third bank may be referred to as a PVT bank, an acquisition bank, and a tracking (integer) bank, respectively. The varactor size corresponding to 1 bit of the third bank is basically the minimum size.

As a request to the digital PLL circuit D, it may be required to lock at a frequency that is narrower than a frequency interval that can be locked by the third bank. In this case, the lower bit is converted to an analog voltage by D / A2 and input to the varactor. The D / A 2 converts Tracking bits (fractional), which are lower bits, into a control voltage of the DCO 1 and controls the varactor of the DCO 1. The LPF 3 removes high frequency components from the analog signal output by the D / A 2 and inputs the analog signal to the varactor of the DCO 1. The retimed reference signal CKR is used as a synchronization signal for D / A2.

  A TDC (Time-to-Digital Converter) 4 measures a difference between pulse edges of the output signal CKV of the DCO 1 and the reference signal FREF after the frequency divider F as a time interval. The output value is a digital value corresponding to the fractional part circumference.

  The sampler 5 synchronizes the rising edge of the reference signal FREF after the frequency divider F with the rising edge of the output signal CKV of the DCO 1 and outputs a retimed reference signal CKR. The entire system operates in synchronization with the reference signal CKR. For example, the reference phase accumulator 6 and the sampler 9 synchronize the data update timing based on the reference signal CKR.

  The reference phase accumulator 6 accumulates the divided data FCW at the timing of the reference signal CKR and outputs it to the phase detector 10. The multiplier 7 multiplies a normalization coefficient for adjusting the DCO frequency division period in the DCO 1 and the output period of the TDC 4.

  The variable phase accumulator 8 counts up by +1 for each rising edge of the output signal CKV of the DCO 1 and outputs the digital value. The sampler 9 outputs the output value from the variable phase accumulator 8 to the phase detector 10 at the rising edge of the reference signal CKR. That is, the number of pulses of the output signal CKV of the DCO 1 in the cycle of the reference signal CKR is measured. This is digital data corresponding to integer division.

  The phase detector 10 compares the output value of the reference phase accumulator 6, the output value of the multiplier 7, and the output value of the sampler 9 by operation, and outputs the result as a phase error to the loop filter 11. The output of the loop filter 11 is input to the gain normalization circuit 12.

  The gain normalization circuit 12 outputs digital signals of PVT bits, Acquisition bits, Tracking (integer) bits, and Tracking (fractional) bits based on the output of the loop filter 11.

  The analog PLL circuit A includes an EXOR type phase comparator 21, a frequency divider 22, a charge pump 23, and a loop filter 24.

  The EXOR type phase comparator 21 receives the reference signal fr and the output signal CKV of the DCO 1 after the frequency divider 22 and outputs analog phase difference signals for these signals together with the charge pump 23. The loop filter 24 receives an analog phase difference signal from the charge pump 23 and removes a high frequency component unnecessary for the phase synchronization operation. The DCO 1 receives an analog phase difference signal from the loop filter 24 and adjusts the output frequency and the output phase.

  The DCO 1 functions as a DCO when the switching control unit S uses the digital phase comparator of the digital PLL circuit D, but when the switching control unit S uses the analog phase comparator of the analog PLL circuit A, the VCO and the DCO Function as.

(Embodiment 1)
Next, switching control according to the first embodiment will be described. DCO1 corresponds to the oscillating unit and outputs an output signal CKV such that the phase difference between the reference signal FREF and the output signal CKV becomes zero. The phase detector 10 corresponds to the digital phase comparison unit and outputs a digital signal indicating a phase difference. The EXOR type phase comparator 21 corresponds to the analog phase comparator, outputs an analog signal indicating a phase difference, corresponds to the least significant bit of the digital signal, and within a phase difference range including 0 as the phase difference. It has a linear characteristic between the phase difference and the analog signal.

  The digital phase detection characteristic is shown in FIG. The phase detector 10 has a step characteristic between the phase difference and the digital signal. The phase difference for one step is the phase difference for the least significant 1 bit.

  The analog phase detection characteristics are shown in FIG. The EXOR type phase comparator 21 has a linear characteristic between the phase difference and the analog signal. The detection range of the phase difference is a range corresponding to the least significant 1 bit of the digital signal and includes 0 as the phase difference.

  In the first lock operation, the switching control unit S performs phase comparison when the phase difference indicated by the digital signal falls within a phase difference range corresponding to the least significant 1 bit of the digital signal and including 0 as the phase difference. Is switched from the phase detector 10 to the EXOR type phase comparator 21.

  The first lock operation process is shown in FIG. The switching control unit S sets the phase comparison subject in the phase detector 10. The gain normalization circuit 12 outputs a digital signal to the DCO 1 in the order of PVT bits, Acquisition bits, and Tracking bits, and performs phased phase acquisition (step S1).

  The switching control unit S detects that the phase difference indicated by the digital signal output from the phase detector 10 falls within a phase difference range corresponding to the least significant 1 bit of the digital signal and including 0 as the phase difference ( Step S2). Then, the switching control unit S holds the digital signal referred to by the DCO 1 (step S3). Further, the switching control unit S switches the subject of phase comparison from the phase detector 10 to the EXOR type phase comparator 21 (step S4).

  That is, after the phase is drawn to a certain degree of accuracy using the digital PLL circuit D, the phase is adjusted to a higher degree of accuracy while maintaining the degree of accuracy using the analog PLL circuit A. . Therefore, it is possible to provide the PLL circuit P that achieves both improvement of C / N and high-speed frequency switching in the first lock operation.

  In the lock operation from unlocking, the switching control unit S performs phase comparison when the phase difference indicated by the analog signal falls outside the range of the phase difference corresponding to the least significant 1 bit of the digital signal and including 0 as the phase difference. Is switched from the EXOR type phase comparator 21 to the phase detector 10.

  FIG. 5 shows a process of locking operation from unlocking. The switching control unit S detects that the phase difference indicated by the analog signal output from the EXOR type phase comparator 21 is out of the phase difference range corresponding to the least significant 1 bit of the digital signal and including 0 as the phase difference. (Step S11). Then, the switching control unit S switches the main subject of the phase comparison from the EXOR type phase comparator 21 to the phase detector 10 and releases the hold of the digital signal in step S3 (step S12).

  Here, if the phase difference does not greatly deviate from the above range, the gain normalization circuit 12 outputs the digital signal of only the tracking bits to the DCO 1 and performs phase acquisition (step S13). ). However, if the phase difference may greatly deviate from the above range, the gain normalization circuit 12 outputs a digital signal in the order of PVT bits, Acquisition bits, and Tracking bits, and performs stepwise phase adjustment. Just pull in. Steps S14 to S16 are the same as steps S2 to S4, respectively.

  That is, when it becomes impossible to ensure the accuracy of the phase pull-in performed using the digital PLL circuit D, the analog PLL circuit is used after performing the phase pull-in to the accuracy of the level using the digital PLL circuit D. Using A, the phase is adjusted to a higher accuracy while maintaining such accuracy. Therefore, it is possible to provide the PLL circuit P that achieves both improvement of C / N and high-speed frequency switching in the locking operation from unlocking.

(Embodiment 2)
Next, switching control according to the second embodiment will be described. The DCO 1 and the phase detector 10 are the same in the first and second embodiments. The EXOR type phase comparator 21 corresponds to the analog phase comparator, outputs an analog signal indicating a phase difference, corresponds to the lower m bits (m> 1) of the digital signal, and includes a phase difference range including 0 as the phase difference Within, it has a linear characteristic between the phase difference and the analog signal.

  The digital phase detection characteristics are the same in the first and second embodiments. The analog phase detection characteristics are shown in FIG. The EXOR type phase comparator 21 has a linear characteristic between the phase difference and the analog signal. The detection range of the phase difference is a range corresponding to the lower m bits (m> 1) of the digital signal and includes 0 as the phase difference. That is, the phase difference detection range (for the lower m bits of the digital signal) of the EXOR type phase comparator 21 is set wider than the phase difference detection accuracy (for the least significant 1 bit of the digital signal) of the phase detector 10. Yes.

  The first lock operation process is the same as in the first and second embodiments. FIG. 7 shows a process of locking operation from unlocking. The switching control unit S corresponds to a phase difference in which the phase difference indicated by the analog signal output from the EXOR phase comparator 21 corresponds to the lower n bits (m> n> 1) of the digital signal and includes 0 as the phase difference. Is detected (step S21). While m = 1 in the first embodiment and m> 1 in the second embodiment, in addition to the first embodiment in the second embodiment, in which direction the phase difference deviates from the above range. Can be provided. Steps S22 to S26 are the same as steps S12 to S16, respectively.

  Since the PLL circuit according to the present invention can achieve both C / N improvement and high-speed frequency switching, the PLL circuit can be applied to a commercial radio device that requires a high C / N and has an external DCO.

P: PLL circuit D: Digital PLL circuit A: Analog PLL circuit S: Switching control unit F: Divider by 2 1: DCO
2: D / A
3: LPF
4: TDC
5: Sampler 6: Reference phase accumulator 7: Multiplier 8: Variable phase accumulator 9: Sampler 10: Phase detector 11: Loop filter 12: Gain normalization circuit 21: EXOR type phase comparator 22: Divider 23: Charge Pump 24: Loop filter

Claims (3)

An oscillator that outputs the output signal such that the phase difference between the reference signal and the output signal is zero;
A digital phase comparator that outputs a digital signal indicating the phase difference;
An analog signal indicating the phase difference is output, and a linear characteristic between the phase difference and the analog signal within the range of the phase difference corresponding to at least one least significant bit of the digital signal and including 0 as the phase difference An analog phase comparator having
When the phase difference indicated by the digital signal falls within the range of the phase difference corresponding to the least significant 1 bit of the digital signal and including 0 as the phase difference, the subject of phase comparison is taken from the digital phase comparison unit. A switching control unit for switching to the analog phase comparison unit;
A PLL circuit comprising: The analog phase comparison unit has a linear characteristic between the phase difference and the analog signal within the range of the phase difference corresponding to the least significant 1 bit of the digital signal,
When the phase difference indicated by the analog signal corresponds to the least significant 1 bit of the digital signal and falls outside the range of the phase difference including 0 as the phase difference, the switching control unit performs the phase comparison subject. The PLL circuit according to claim 1, wherein the analog phase comparison unit is switched to the digital phase comparison unit. The analog phase comparison unit has a linear characteristic between the phase difference and the analog signal within the range of the phase difference corresponding to the lower m bits (m> 1) of the digital signal,
When the phase difference indicated by the analog signal corresponds to the lower n bits (m>n> 1) of the digital signal and falls outside the range of the phase difference including 0 as the phase difference, the switching control unit The PLL circuit according to claim 1, wherein the main body of phase comparison is switched from the analog phase comparison unit to the digital phase comparison unit.

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