KR20110070719A - All digital phase locked loop - Google Patents

Abstract

PURPOSE: A time to digital converter(TDC) and a complete digital phase locked loop including the same are provided to detect minute phase error required in compensating phase difference between a DCO clock and a reference clock, by installing the TDC. CONSTITUTION: A complete digital PLL(100) accumulates a frequency setting word value and a phase of a DCO clock. A phase counter(200) detects minute phase difference between a reference clock and a rising edge re-timed clock. A phase detector(300) compensates phase difference between a FSW(Frequency setting word) and the DCO clock. The phase detector detects a digital phase error value. A digital loop filter(400) controls PLL loop operation characteristics by filtering the digital phase error value. A lock detector(500) generates a lock indication signal. A digital controlled oscillator(600) controls the frequency of the DCO clock according to the output of the digital loop filter. A re-timed clock generator(700) outputs re-timed clocks.

Description

Time-to-digital converter and all-digital phase locked loop including the same

The present invention relates to an all-digital phase locked loop. In particular, the present invention relates to a time-to-digital converter capable of reducing power consumption, noise, and area to be suitable for a mobile communication terminal having a strict performance standard. It is about.

The present invention is derived from a study performed as part of the IT source technology development project of the Ministry of Knowledge Economy [Task Management Number: 2008-F-008-02, Title: Development of Advanced Digital RF technology for the next generation wireless convergence terminal].

A charge pump phase locked loop (PLL) has been mainly used to design existing RF frequency synthesizers for multiband mobile communication, and analog circuit design technology is integrated in the charge pump PLL.

Therefore, due to the analog circuit and the analog signal characteristics, an additional analog / RF library is required in addition to the design library provided by the standard digital CMOS process, and thus it is difficult to integrate with the digital baseband signal processing block using the digital CMOS process.

Recently, nanometer-class digital CMOS processes have been developed due to the development of process technology, and digital baseband signal processing blocks are rapidly being developed using nanoscale digital CMOS processes.

In line with the development of such nanotechnology, digital circuits can be easily adapted to the process technology to be manufactured with almost no redesign, but analog / RF circuits have a problem of having to redesign whenever the process technology changes. In addition, as the CMOS process technology develops to the nano level, the operating voltage also decreases.

Therefore, since it takes a lot of time and money to improve the various problems in the analog / RF integrated circuit design in the nano-scale digital CMOS process, the research and development on the digital RF to digitize the analog / RF circuit block gradually becomes active have.

In particular, the frequency synthesizer in the RF transceiver is a part that can be fully digitized. Digital PLL frequency synthesizer technology has a long history, but it is rarely used as a local oscillator for RF transceiver for mobile communication that requires high quality phase noise due to poor phase noise and jitter characteristics.

However, in recent years, a new type of all digital PLL (ADPLL) has been developed by applying digital PLL technology to a frequency synthesizer for mobile communication. The difference between digital PLLs and ADPLLs in the past lies in the Digitally Controlled Oscillator (DCO). In the past, DCOs were implemented using digital logic, while nowadays DCOs are implemented using LC resonators.

Therefore, LC resonant DCO is characterized by better phase noise and jitter noise than DCO using digital logic.

Since the LC resonant DCO adjusts the oscillation frequency by controlling the amount of change in capacitance of the LC resonator, the capacitor bank is divided into a coarse adjustment bank and a fine adjustment bank. The DCO's coarse adjustment bank is used to quickly lock the PLL to the desired PLL frequency. The coarse adjustment bank is transferred to the fine adjustment bank by the mode switching signal when the core adjustment is approached to the target PLL frequency. Fine tracking locks the target PLL frequency.

The microphase error (ε) used for fine tracking is generated by a time-to-digital converter (TDC), and the minute phase difference between the reference clock and the DCO clock is reduced to the microphase error (ε). Thus compensated in the arithmetic phase detector.

The phase noise performance of the existing digital PLL is determined by the resolution of the microphase error ε that the TDC can detect. That is, the higher the fine phase error detection resolution of TDC, the better the phase noise, and the fine phase error detection resolution is determined by the minimum delay element delay time of the inverter chain constituting the TDC.

However, since the delay chain of the conventional TDC is operated using a DCO clock having a high frequency, it has a disadvantage of generating a large power consumption and noise.

As described above, the conventional DCO is divided into a coarse adjustment bank and a fine adjustment bank so that when the digital PLL is locked in the coarse locking mode, a lock indication signal is required to switch from the coarse adjustment bank of the DCO to the fine adjustment bank. . The circuit used at this time is a lock detector.

Although many lock detectors have been developed in existing analog PLLs, many lock detectors have been developed for digital PLLs, and have a disadvantage of using a lookup table that uses a memory and has a complicated structure.

In addition, conventional all-digital PLLs are structurally narrowband, making them difficult to use in other wider bandwidth applications.

In the present invention, the DCO clock is operated using a signal that is timed at a low frequency, thereby providing the same phase error detection capability as in the prior art, which can reduce power consumption, noise, and area, and includes the same. We want to provide a fully digital PLL.

In addition, a lock detector for an all-digital PLL having a simple structure consisting of a delay circuit and a comparison circuit is proposed instead of using a memory and a complex lookup table.

As a means for solving the above problems, according to the first aspect of the present invention, a full digital phase locked loop accumulates a frequency of a set word value and a phase of a digital controlled oscillator (DCO) clock and fines between a reference clock and a timed clock. A phase counter for detecting a phase difference; A phase detector for detecting a digital phase error value by compensating for a phase difference between the frequency setting word and the DCO clock according to a fine phase difference between the reference clock and the retimed clock; A digital loop filter for filtering the digital phase error value and controlling a PLL loop operating characteristic; A lock detector detecting a time point at which the output of the digital loop filter is constant and generating a lock indication signal; A digitally controlled oscillator in which a frequency of the DCO clock is changed in accordance with an output of the digital loop filter while switching an operation mode according to the lock indication signal; And a timed clock generator for generating the timed clock after the DCO clock is retimed at a low frequency.

The timed clock generator may include: a first latch circuit configured to generate a rising edge timed clock by obtaining and outputting a signal value of the reference clock in synchronization with a rising edge of the DCO clock; And a second latch circuit synchronized with a falling edge of the DCO clock to acquire and output a signal value of the reference clock to generate a falling edge timed clock.

The phase counter includes: a reference phase accumulator for accumulating a phase of the frequency setting word according to the rising edge timed clock; A variable phase accumulator for accumulating a phase of the DCO clock; A sampler for detecting a change amount of the DCO clock by sampling a value of the variable phase accumulator according to the rising edge timed clock; And a time to digital converter (TDC) for detecting a phase difference between the reference clock and the rising edge timed clock.

The TDC includes a delay chain for delaying the phase of the reference clock; A sampler sampling the output of the delay chain according to the rising edge timed clock and the falling edge timed clock, respectively; An edge detector which detects a time point at which the output value of the sampler changes, and obtains a microphase difference between the reference clock and the rising edge timed clock and a microphase difference between the reference clock and the falling edge timed clock; Calculate a DCO clock period by subtracting and doubling the microphase difference between the reference clock and the rising edge timed clock and the microphase difference between the reference clock and the falling edge timed clock, and calculating the DCO clock period using the DCO clock period. And a normalized multiplier for normalizing and outputting a microphase difference between a reference clock and the rising edge timed clock.

The normalization multiplier includes: a subtractor for subtracting a microphase difference between the reference clock and the rising edge timed clock and a microphase difference between the reference clock and the falling edge timed clock; An absolute value obtainer for obtaining an absolute value of the output of the subtractor; A multiplier for obtaining the DCO clock period by doubling the output of the absolute value obtainer; And a multiplier for multiplying a fine phase difference between the reference clock and the rising edge timed clock by the inverse of the DCO clock period. A DCO clock cycle averaging unit for averaging the DCO clock cycles obtained through the multiplier; A multiplexer for selecting and outputting one of a DCO clock period obtained through the multiplier and a DCO clock period averaged through the DCO clock period averaging unit; And a memory configured to store the DCO clock period selected through the multiplexer.

The TDC further includes a delay chain for delaying a phase of the reference clock; A sampler sampling the output of the delay chain according to the rising edge timed clock; An edge detector which detects a time point at which the output value of the sampler changes, and obtains a microphase difference between the reference clock and the rising edge timed clock; And calculating a DCO clock period by subtracting the maximum value and the minimum value of the microphase difference between the reference clock and the rising edge timed clock, and calculating the DCO clock period using the DCO clock period, between the reference clock and the rising edge timed clock. It may include a normalized multiplier for normalizing and outputting the microphase difference.

The normalized multiplier includes a maximum and minimum detector for detecting a maximum value and a minimum value of a microphase difference between the reference clock and the rising edge timed clock; A subtractor for subtracting the maximum value and the minimum value to obtain the DCO clock period; And a multiplier for multiplying the inverse of the DCO clock period by a microphase difference between the reference clock and the rising edge timed clock.

The normalized multiplier includes: a multiplexer for selecting and outputting one of a DCO clock period and a preset DCO clock period obtained through the subtractor; And a memory configured to provide an output of the multiplexer to the multiplier.

The lock detector includes: a comparison unit for comparing the output of the digital loop filter bit by bit; A delay cell block generating a plurality of delay signals having different phases from the output of the comparator, and logically combining the plurality of delay signals and the output of the comparator; And a detector configured to detect a time point at which the output value of the delay cell block changes, and output the lock indication signal.

The comparator comprises: a plurality of delayers for delaying the output of the digital loop filter bit by bit; A plurality of comparators for bit-by-bit comparison between the output of the digital loop filter and the output of the plurality of delayers; And an operator configured to perform an OR operation on the outputs of the plurality of comparators.

The delay cell block may include a delay chain configured to delay a phase of an output of the comparator; And an operator configured to perform an OR operation on the output of the delay chain and the output of the comparator.

The detection unit includes a latch circuit for detecting a time point at which the output value of the delay cell block changes; And a pulse generator for outputting a lock instruction signal in response to the output of the latch circuit.

The digitally controlled oscillator selects one of a coarse adjustment bank, an intermediate adjustment bank, and a fine adjustment bank according to the lock indication signal, and varies the capacitance value of the selected adjustment bank according to the output of the digital loop filter. Frequency can be controlled.

As a means for solving the above problems, according to a second aspect of the present invention, a TDC for an all-digital phase locked loop includes: a delay chain for delaying a phase of a reference clock; A sampler configured to receive a rising edge timed clock and a falling edge timed clock that synchronize the reference clock with rising and falling edges of the DCO clock, and sample the output of the delay chain; An edge detector which detects a time point at which the output value of the sampler changes, and obtains a microphase difference between the reference clock and the rising edge timed clock and a microphase difference between the reference clock and the falling edge timed clock; A DCO clock period is calculated by subtracting and doubling the microphase difference between the reference clock and the rising edge timed clock and the microphase difference between the reference clock and the falling edge timed clock, and calculating the DCO clock period using the DCO clock period. And a normalized multiplier for normalizing and outputting a microphase difference between a clock and the rising edge timed clock.

The normalization multiplier includes: a subtractor for subtracting a microphase difference between the reference clock and the rising edge timed clock and a microphase difference between the reference clock and the falling edge timed clock; An absolute value obtainer for obtaining an absolute value of the output of the subtractor; A multiplier for obtaining the DCO clock period by doubling the output of the absolute value obtainer; And a multiplier for multiplying the inverse of the DCO clock period by a microphase difference between the reference clock and the rising edge timed clock.

As a means for solving the above problems, according to a third aspect of the present invention, a TDC for an all-digital phase locked loop includes: a delay chain for delaying a phase of a reference clock; A sampler that receives a timed clock that synchronizes the reference clock to an output of a digitally controlled oscillator (DCO) and samples the output of the delay chain; An edge detector which detects a time point at which the output value of the sampler changes, and obtains a microphase difference between the reference clock and the rising edge timed clock; And calculating a DCO clock period by subtracting the maximum value and the minimum value of the microphase difference between the reference clock and the rising edge timed clock, and calculating the DCO clock period using the DCO clock period, between the reference clock and the rising edge timed clock. It may include a normalized multiplier for normalizing and outputting the microphase difference.

The normalized multiplier includes a maximum and minimum detector for detecting a maximum value and a minimum value of a microphase difference between the reference clock and the rising edge timed clock; A subtractor for subtracting the maximum value and the minimum value to obtain the DCO clock period; And a multiplier for multiplying the inverse of the DCO clock period by a microphase difference between the reference clock and the rising edge timed clock.

As a means for solving the above problem, according to a fourth aspect of the present invention, a lock detector for a full digital phase locked loop receives a plurality of bit signals from a digital loop filter, and determines whether each of the plurality of bit signals is locked. A comparator for outputting one bit signal including related information; A delay cell block outputting one clock signal by combining the one bit signal and the signal delaying the one bit signal by a predetermined time; And a detector configured to detect a signal value change point of the one clock signal and output a lock instruction signal for switching the operation mode of the digitally controlled oscillator.

As described above, the all-digital PLL of the present invention has a TDC capable of providing the same phase error detection capability as the conventional method but reducing power consumption, noise, and area. Make it possible to detect microphase errors. Accordingly, the TDC may have a power consumption, noise, and area reduced by about 50%, and the all-digital PLL including the same may also have a reduced power consumption, noise, and area.

In addition, instead of using a complex lookup table that uses memory, a simple structure such as a delay circuit and a comparison circuit can detect a fixed point of the PLL loop and generate a lock indication signal. And further reduce the area.

1 is a block diagram of an all-digital PLL according to an embodiment of the present invention.
2 is a diagram illustrating a detailed configuration of a phase counter and a phase detector according to an embodiment of the present invention.
3A illustrates a detailed configuration of a TDC according to an embodiment of the present invention.
3B is a view for explaining the operation of the TDC according to an embodiment of the present invention.
4A is a diagram illustrating a detailed configuration of a TDC according to another embodiment of the present invention.
4B is a diagram for explaining an operation of a TDC according to another embodiment of the present invention.
5 and 6 are views for explaining in detail the operating performance of the TDC according to an embodiment of the present invention.
7 illustrates a detailed configuration of a digital loop filter, a lock detector, and a DCO according to an embodiment of the present invention.
8 is a diagram illustrating a detailed configuration of a lock detector according to an embodiment of the present invention.
9 is a diagram illustrating a detailed configuration of a comparator, a delay cell block, and a detector according to an embodiment of the present invention.
10A through 10E are diagrams for describing an operation of a lock detector according to an exemplary embodiment of the present invention.
FIG. 11A is a diagram illustrating frequency fixing characteristics of a digital PLL according to an embodiment of the present invention. FIG.
11B illustrates the output spectrum of a digital PLL according to an embodiment of the present invention.
12 is a diagram illustrating a detailed configuration of a timed clock generating unit according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, in describing in detail the operating principle of the preferred embodiment of the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In order to clearly illustrate the present invention, parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification.

In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

1 is a block diagram of an all-digital PLL according to an embodiment of the present invention.

Referring to FIG. 1, the all-digital PLL 100 accumulates a phase of a frequency setting word (FSW) and a DCO clock (CKV), and stores a reference clock FREF and a rising edge timed clock. Digital phase error value by compensating the phase difference between FSW and DCO clock (CKV) according to the microphase difference between the phase counter 200 and the reference clock FREF and the rising edge timed clock CKRp that detects the microphase difference between CKRp). A phase detector 300 for detecting a signal, a digital loop filter 400 for filtering the digital phase error value, and controlling a PLL loop operation characteristic, and detecting a time point at which the output of the digital loop filter 400 is constant. Digital control for switching the operation mode according to the lock detector 500 generating the LD and the lock indication signal LD and controlling the frequency of the DCO clock CKV in accordance with the output of the digital loop filter 400. Digital Controlled Oscillator DCO) 600, and a retimed clock generator 700 that oversamples the DCO clock CKV at a low frequency to output retimed clocks CKRp and CKRn.

In this case, the retimed clock generator 700 sets the rising edge timed clock CKRp and the reference clock FREF in synchronization with the rising edge of the DCO clock CKV to the DCO clock CKV. One or more of the falling edge timed clocks (CKRn) synchronized with the falling edges of may be output. The rising edge timed clock CKRp is used as a clock for synchronizing signal flow inside the all-digital PLL 100, and the falling edge timed clock CKRn is one period of the DCO clock CKV. Used as a clock to calculate (Tv).

2 is a diagram illustrating a detailed configuration of a phase counter and a phase detector according to an embodiment of the present invention.

2, the phase counter 200 accumulates the reference phase accumulator 210 and the DCO clock CKV which repeatedly accumulate the phase of the FSW according to the rising edge timed clock CKRp. A variable phase accumulator 220 for sampling according to the timed clock CKRp and detecting a change amount of the DCO clock CKV, and a TDC for detecting a phase difference between the reference clock FREF and the rising edge timed clock CKRp ( Time to Digital Converter) 230 and the like.

In this case, the variable phase accumulator 220 samples an accumulator 221 that accumulates the DCO clock CKV and an output of the accumulator 221 according to a rising edge timed clock CKRp to generate a second bit of i-bit. And a sampler 222 generating an integer word value W _I2 , and the TDC 230 delays a phase of the reference clock FREF little by little to generate a plurality of delay signals having different phases. Changes in the output values of the sampler 232 and the sampler 232 for sampling the chain 231 and the output of the delay chain 231 according to the rising edge timed clock CKRp and the falling edge timed clock CKRn, respectively. By detecting the time point, the microphase difference ε _P (hereinafter referred to as rising edge phase error) between the reference clock FREF and the rising edge timed clock CKRp and the reference clock FREF and falling edge timed clock CKRn ) to an edge detector 233 for obtaining a fine phase difference (ε _N) (hereinafter, the falling edge phase error) between the rising and Phase error (ε _P) and the trailing edge phase error (ε _N) subtraction operations, and 2 is a multiple by DCO clock cycles (Tv) calculated, and the rising edge phase error (ε _P) by the DCO clock cycles (Tv) a normalization of It may include a normalized multiplier 234 and the like output.

Hereinafter, the operation of the phase counter 200 will be described.

Unlike the conventional FSW and the DCO clock (CKV), the phase counter 200 has a rising edge timed clock CKRp and a falling edge timed clock CKRn that have been retimed at a low frequency with the DCO clock CKV. Get more input.

The reference phase accumulator 210 divides the FSW into integer digital word i (i is a natural number) bit and a fractional digital word j (j is a natural number) bit, and then repeats its phase according to a rising edge timed clock (CKRp). Accumulate to generate a first integer word value W _I1 of i bits and a first fractional word value W _F1 of j bits. In addition, the variable phase accumulator 220 accumulates the DCO clock CKV and samples the second phase word value W _F2 of j bits by sampling according to the rising edge timed clock CKRp.

At the same time, the TDC 230 samples the reference clock FREF into the rising edge timed clock CKRp and the falling edge timed clock CKRn, respectively, to raise the rising edge phase error ε _P and the falling edge phase error. After obtaining (ε _N ), subtracting and doubling to calculate the DCO clock period Tv, and normalizing the rising edge error ε _P to the DCO clock period Tv to normalize the second decimal number of j bits. Generates the word value W _F2 .

As described above, it can be seen that the phase counter 200 of the present invention is operated using the new signal, that is, the timed clocks CKRp and CKRn which have re-timed the DCO clock CKV at a low frequency.

In particular, the TDC 230 according to the present invention does not detect a phase difference between the reference clock FREF and the DCO clock CKV, but instead of detecting a phase difference between the reference clock FREF and the rising edge timed clock CKRp. It can be seen that the detection. However, since the timed clocks CKRp and CKRn are synchronized with the DCO clock CKV, the TDC 230 of the present invention may have the same phase error detection capability as that of the conventional TDC. This will be described in more detail with reference to FIGS. 5 and 6 below.

That is, the TDC 230 of the present invention operates by using the timed clocks CKRp and CKRn oversampling the low frequency reference clock FREF with the DCO clock CKV, thereby detecting the same phase error. It offers the ability to reduce power consumption and noise.

2, the phase detector 300 includes a first adder 310 and a first decimal word value for obtaining a difference between a first integer word value W _I1 and a second integer word value W _I2 . The third adder 330 that adds the outputs of the second adder 320 and the first adder 310 and the second adder 320 to obtain the sum of (W _F1 ) and the second decimal word value W _F2 . And a register 340 synchronized with the rising edge timed clock CKRp to output the output of the third adder 330 to the digital loop filter 400.

Hereinafter, the operation of the phase detector 300 will be described.

First, the first adder 310 has a first integer word value W _I1 obtained through the reference phase accumulator 210 and a second integer word value W _I2 obtained through the variable phase accumulator 220. Subtract). In this case, the subtracted integer word value (W _I = W _I1 -W _I2 ) is input to the digital loop filter 400 through the third adder 330 and the register 340, and the digital loop filter ( 400 scales it down and provides it to the DCO 600 so that the coarse adjustment bank and the intermediate adjustment bank included in the DCO 600 are the subtracted integer word values (W _I = W _I1 -W _I2 ). To be controlled by

At the same time, the second adder 320 adds a first small word value W _F1 obtained through the reference phase accumulator 210 and a second small word value W _F2 through the TDC 230. After operation, the rounded 1-bit signal ov is provided to a carry input of the first adder 310, and the j-bit added arithmetic decimal word value (W _F = W _F1 + W _F2 ). Is supplied to the digital loop filter 400 through the third adder 330 and the register 340. Accordingly, the digital loop filter 400 scales it down and provides it to the DCO 600 so that the intermediate adjustment bank and the fine adjustment capacitor bank included in the DCO 600 are added to the fractional word value W _F. = W _F1 + W _F2 ).

If the word width W _I of the integer digital value is 8 bits and the word width W _F of the fractional digital value is 15 bits, the digital phase error value W _I + W _{F of} the phase detector 300 is A total of 23 bits will be described, and the operation of the all-digital PLL 100 will be described by applying a total of 23 digital phase error values (W _I + W _F ).

The fully digital PLL 100 sets the PLL frequency by the digital value of the FSW, and the PLL loop continuously tracks the digital phase error value of the phase detector 300 so that the PLL frequency is locked by the PLL frequency set by the FSW. .

The phase detector 300 receives the digital phase values of the FSW and DCO clocks (CKVs) by using the phase counter 200 operated by receiving the FSW, DCO clocks (CKVs) and the timed clocks (CKRp, CKRn). By accumulating and performing arithmetic operations, a phase error between the FSW and the DCO clock (CKV) is detected.

The detected phase error is provided to the digital loop filter 400 as a 23-bit digital signal in binary binary form, and the digital loop filter 400 scales down the 23-bit digital phase error value into smaller bits. Output

Then, the lock detector 500 analyzes the m bit output signal output from the digital loop filter 400 to generate a lock indication signal for switching the operation mode of the DCO 600, and the DCO 600 indicates the lock indication. The frequency of the DCO clock (CKV) is adjusted by selecting one of the coarse adjustment capacitor bank, the intermediate adjustment bank, and the fine adjustment bank according to the signal, and controlling the capacitor value of the selected bank according to the m bit output signal. do.

As such, when the frequency of the DCO clock CKV is continuously changed according to the digital phase error value detected by the phase detector 300, the all-digital PLL 100 is locked at the frequency set by the FSW value.

3A illustrates a detailed configuration of a TDC according to an embodiment of the present invention.

Referring to FIG. 3A, the TDC 230 may include a delay chain 231, a sampler 232, an edge detector 233, a normalization multiplier 234, and the like.

The delay chain 231 may include a plurality of delay elements connected in series, and the sampler 232 may sample an output of the delay chain 231 according to a rising edge timed clock CKRp. A first register array 321 having a plurality of registers REG for outputting and a register REG for sampling and outputting the output of the delay chain 231 according to the falling edge timed clocks CKRn. It may include a second register array 322 having a plurality. In this case, the register REG may be implemented as a D-FF.

The edge detector 233 detects a change point of the output value of the first register array 321 to obtain a rising edge phase error ε _P and an output value of the second register array 322. A second edge detector 332 or the like for detecting the change time point and obtaining the rising edge phase error ε _P may be included.

The normalization multiplier 234 subtracts the rising edge phase error ε _P and the falling edge phase error ε _N and outputs a subtractor 341 and an output value ε _N -ε _P of the subtractor 341. Absolute value obtainer (ABS, 342) for obtaining the absolute value of the multiplier; The DCO clock period averager 344 obtaining the average value of the DCO, the DCO clock period Tv obtained through the multiplier 343 and the DCO clock period averager 344 obtained through the multiplier 343 according to the multiplexer control signal ctrl. A multiplexer (MUX, 345) for selecting and outputting one of the clock cycle average values (Tv_avg), a memory (346) for storing the DCO clock period selected through the multiplexer (345), and the rising edge phase error (ε _P ). product of generating the second memory decimal word values (W _F2) multiplied by the reciprocal of the DCO clock period is stored in 346 and the output It may include a group (347).

In this case, the normalization multiplier 234 may obtain an average value of the DCO clock period through the DCO clock period averaging unit 344, and may have an increased linear characteristic by normalizing the rising edge phase error ε _P. In addition, the multiplexer control signal ctrl is activated when the operation mode of the DCO 600 is in the fine adjustment mode, and the multiplexer 345 outputs the average value of the DCO clock period in response thereto, so that the normalization multiplier 234 While the DCO 600 operates in the fine adjustment mode, the rising edge phase error ε _P can be normalized according to the average value of the DCO clock period.

Hereinafter, the operation of the TDC 230 will be described with reference to FIG. 3B. In FIG. 3B, D [0] to D [10] mean an output signal output from a plurality of delay elements Delay in the delay chain 231.

First, the delay chain 231 gradually delays the phase of the reference clock FREF by the delay time of one delay element to the inputs of the first and second register arrays 321 and 322.

The first register array 321 is synchronized to the rising edge timed clock CKRp to sample the output of the delay chain 231 to correspond to the phase difference between the reference clock FREF and the rising edge timed clock CKRp. Outputs TDC_Qp having a value (10000000001), and the second register array 322 is synchronized to the falling edge timed clock CKRn to sample the output of the delay chain 231 to reference the reference clock FREF and falling edge. TDC_Qn having a value 11110000001 corresponding to the phase difference of the timed clock CKRn is output. In this case, the output signals TDC_Qp and TDC_Qn of the first and second register arrays 321 and 322 may have a pseudo thermometer code form.

The first and second edge detectors 331 and 332 then detect when the output value changes of the first and second register arrays 321 and 322 (ie, until the signal value changes from " 1 " to " 0 "). detecting the number of "1"), obtains a rising edge and a falling edge phase error (ε _P, ε _N). That is, the first and second edge detectors 331 and 332 have a rising edge phase error (ε _P = 1) and a falling edge phase error (ε _N = 4) in response to TDC_Qp (= 10000000001) and TDC_Qn (= 11110000001). Outputs The detection operations of the first and second edge detectors 331 and 332 may be represented by Table 1 below. Table 1 shows an example of a detection operation performed when the first edge detector 331 receives 32 signals from the first register array 321 to generate a 6-bit output signal, and EPnum is a rising edge. It means the value of phase error.

Finally, the normalized multiplier 234 subtracts the rising edge and falling edge phase errors (ε _P , ε _N ) and multiplies by two to obtain a DCO clock period Tv, and then through the DCO clock period Tv. The second edge word value W _f2 is obtained by dividing the rising edge phase error ε _P. The operation of the normalization multiplier 234 may be represented by Equation 1 below.

[Equation 1]

W _F2 = ε _P / Tv

Tv = 2 ⅹ | ε _P -ε _N |

As described above, the TDC according to the embodiment of the present invention uses the timed clocks CKRp and CKRn oversampling the low frequency reference clock FREF with the DCO clock CKV. It is possible to detect the microphase error required for the phase difference compensation between CKV).

In the above, the TDC is operated using two timed clocks CKRp and CKRn. However, if necessary, the TDC may be operated using only one timed clock CKRp or CKRn.

4A illustrates a detailed configuration of a TDC according to another embodiment of the present invention. The TDC of FIG. 4A may be operated using only a rising edge timed clock CKRp.

4A, the TDC 230 slightly delays the phase of the reference clock FREF to generate a plurality of delay signals having different phases from each other. Detects the change of the output value of the sampler 232 and the sampler 232 that respectively sample the output according to the rising edge timed clock CKRp to detect the fine point between the reference clock FREF and the rising edge timed clock CKRp. An edge detector 233 for acquiring a phase difference ε _P (that is, a rising edge phase error), and a subtraction operation after obtaining the maximum and minimum values of the rising edge phase error ε _P and subtracting the DCO clock period Tv. And a normalization multiplier 234 for normalizing and outputting the rising edge error ε _{P in} the DCO clock period Tv.

More specifically, the delay chain 231 may include a plurality of delay elements (Delay) connected in series, the sampler 232 is the delay chain 231 according to the rising edge timed clock (CKRp) A plurality of registers (REG) and the like to sample the output of the output may include. In this case, the register REG may be implemented as a D-FF.

And the minimum value (min (ε) of the normalized multiplier 234 is the rising edge phase error maximum value detector 351, the rising edge phase error (ε _P) for detecting the maximum value (max (ε)) in the (ε _P) A subtractor 353 for subtracting the maximum value max (ε) and the minimum value min (ε) to calculate a DCO clock period Tv, and the DCO clock. A memory 355 for storing a period Tv, a multiplexer (hereinafter, MUX) 356 for selecting and outputting one of a DCO clock period stored in the memory 355 and a preset DCO clock period, and the rising edge error and a multiplier 357 that generates and outputs a second fractional word value W _F2 by multiplying (ε _P ) by the inverse of the DCO clock period selected by the MUX 356.

In addition, the normalization multiplier 234 updates the DCO clock period Tv obtained through the subtractor 353 in the memory 355 only when the operation mode of the DCO 600 is the fine adjustment mode. The DCO clock period Tv stored in the memory 355 may include the DCO clock period Tv and the DCO clock period Tv obtained through the subtractor 353 as described above. It can be one of the mean values.

In addition, the multiplexer control signal ctrl of FIG. 4A is also activated when the operation mode of the DCO 600 is fine-tuned, and the MUX 356 outputs a preset DCO clock period in response to the normalization multiplier 234. ) Allows the rising edge phase error ε _P to be normalized according to a preset DCO clock period while the DCO 600 operates in the fine adjustment mode. The preset DCO clock period is determined by the PLL frequency set by the FSW.

Hereinafter, the operation of the TDC 230 will be described with reference to FIG. 4B. In FIG. 4, D [0] to D [10] mean an output signal output from a plurality of delay elements Delay in the delay chain 231.

First, when the reference clock FREF is input to the delay chain 231, the reference clock FREF is gradually delayed by a delay time of one delay element while passing through the delay chain 231, and then sampler 232. Is provided as input.

The sampler 232 is then synchronized to the rising edge timed clock CKRp through a plurality of registers REG to sample the output of the delay chain 231 to thereby reference the reference clock FREF and the rising edge timed clock CKRp. Outputs TDC_Qp having a value corresponding to the phase difference of (e.g., 10000000001), and the edge detector 233 detects an output value change point of the sampler 232 (i.e., the signal value is "1" to "0"). detects the number of 1 "" on until it changes to "), to obtain the rising edge phase error (ε _P).

Finally, the normalized multiplier 234 detects the maximum value (max (ε)) and minimum value (min (ε)) of the rising edge phase error ε _P , and subtracts them to calculate the DCO clock period Tv. The second decimal word value W _F2 is obtained by normalizing the rising edge phase ε _{P with the} DCO clock period Tv. The operation of the normalization multiplier 234 may be represented by Equation 2 below.

&Quot; (2) "

W _F2 = ε / Tv

Tv = max (ε) -min (ε)

5 and 6 are views for explaining in detail the operating performance of the TDC according to an embodiment of the present invention.

In Figure 5 (a) is a conventional TDC, (b) is a TDC according to an embodiment of the present invention, (c) is a microphase error detected through the TDC according to the prior art, ( d) shows the microphase errors detected through the TDC according to an embodiment of the present invention, respectively, in Figure 6 (a) is an internal signal timing diagram of the TDC according to the prior art, (b) is in the present invention The internal signal timing diagrams of the TDCs according to an embodiment are respectively shown.

Referring to FIGS. 5A and 5B, the conventional TDC 800 directly uses the DCO clock CKV and the reference clock FREF to provide a phase difference between the DCO clock CKV and the reference clock FREF. However, the TDC 230 of the present invention uses the timed clocks CKRp and CKRn and the reference clock FREF oversampled the low frequency reference clock FREF with the DCO clock CKV. It can be seen that the phase difference between the clock CKV and the reference clock FREF is detected.

Therefore, since the conventional TDC 800 must operate at high speed according to the DCO clock (CKV) (for example, 2.17 GHz), it has a large power consumption and noise, but the TDC 230 of the present invention has a low frequency reference clock. Can operate at slower speeds according to the retimed clocks CKRp and CKRn (e.g. 30.72 MHz) oversampling (FREF) to the DCO clock (CKV), resulting in reduced power consumption and noise. . For reference, since the power consumption of the digital PLL is mostly consumed by the TDC and the DCO, reducing the power consumption of the TDC contributes significantly to reducing the power consumption of the entire PLL.

In addition, since the TDC 230 of the present invention uses the timed clocks CKRp and CKRn synchronized to the DCO clock CKV as described above, the TDC 230 shown in FIGS. As described above, the microphase error ε between the reference clock FREF and the DCO clock CKV and the microphase error ε between the reference clock FREF and the rising edge timed clock CKRp are the same. Has a value. That is, the TDC 230 of the present invention may have the same phase error detection capability as the conventional TDC 800.

Hereinafter, the microphase error detection process of the conventional TDC 800 and the TDC 230 of the present invention will be compared with reference to FIGS. 5C and 6A as follows.

First, referring to FIGS. 5C and 6A, the conventional TDC 800 inputs the DCO clock CKV to the delay chain 810 so that the DCO clock CKV is a delay element. Phase delays through the delay chain 810 by t _delays .

The sampler 820 samples the output of the delay chain 810 by using the reference clock FREF, and the edge detector 830 detects a change point of the sampling result so that the rising edge (t _r ) and the falling edge ( It is obtained by falling edge time: t _f ). At this time, the rising edge t _r is a variable for measuring the time difference between the rising edge of the DCO clock CKV and the rising edge of the reference clock FREF, and the falling edge t _f is the falling edge of the DCO clock CKV. It is a variable for measuring the time difference between the falling edge and the rising edge of the reference clock FREF.

For example, if the edge detector 830 refers to FIG. 5C, the rising edge t _r is the number of 1s until the sampling result of the sampler 820 changes from "1" to "0". The falling edge t _f may be represented by an integer value of 7 according to the number of 1s until the sampling result of the sampler 820 changes from "0" to "1".

Then, the normalization multiplier 840 calculates the DCO clock period Tv and the microphase error ε according to Equation 3 below, and divides the microphase error ε by the DCO clock period Tv to represent a fractional word. Obtain the value W _F2 .

&Quot; (3) "

Tv = 2 ⅹ | △ t _r- △ t _f |

ε _r = Tv- △ t _r

W _F2 = ε = (Tv-Δt _r ) / Tv

In this case, since the microphase error ε and the DCO clock period Tv may be represented by the number of delay elements, according to Equation 3, the conventional TDC 800 corresponds to the two period DCO clock CKV. It can be seen that the number of delay elements must be provided to accurately measure the DCO clock period Tv.

Subsequently, referring to FIGS. 5D and 6B, the TDC 230 according to the present invention will be described in more detail as follows.

The TDC 230 of the present invention inputs the reference clock FREF into the delay chain 231 instead of the DCO clock CKV, so that the reference clock FREF is delayed by one delay element (t _delay ). 231) to be gradually delayed in phase.

The sampler 232 samples the output of the delay chain 231 using the rising edge timed clock CKRp and the falling edge timed clock CKRn, and the edge detector 233 detects a change point of the sampling result. To obtain the values of rising edge and falling edge phase errors (ε _P , ε _N ).

After the normalization multiplier 234 obtains the DCO clock period Tv from the rising edge and the falling edge phase errors ε _P and ε _N according to Equation 1 (or Equation 2), the DCO clock period The second decimal word value W _F2 is obtained by dividing the rising edge phase error ε _P through Tv.

Referring to FIG. 5D, the rising edge error ε _P is an integer of 7 depending on the number of 1s until the sampling result of the first register array 321 changes from "1" to "0". It can be expressed as a value, which corresponds to the number of seven delay elements, and therefore, the phase error ε _P and ε _N and the DCO clock period Tv of the present invention are also expressed as the number of delay elements.

However, the TDC 230 of the present invention needs only the number of delay elements capable of measuring a maximum of one period in order to measure the DCO clock period Tv as expressed in Equation 1 (or Equation 2). Therefore, compared to the conventional TDC 800, the number of delay elements can be reduced by about 50%, and accordingly, power consumption, noise, and area can be reduced by about 50%.

The number of delay elements required by the TDC 230 of the present invention is ideally expressed as shown in Equation 4 below, but in practice, a timed clock generator that generates the timed clocks CKRp and CKRn. A delay element corresponding to the delay time of the latch circuit of 700 may be added and expressed as shown in Equation (5).

&Quot; (4) "

[Equation 5]

At this time, Δt _delay is a delay time of the delay element, and Δt _{DF / F} is a delay time of the latch circuit provided in the timed clock generation unit.

As described above, in the case of using the conventional TDC 800, the number of delay elements corresponding to two cycles (2 × Tv) of the DCO clock CKV is required to measure the DCO clock period Tv. In the case of using the TDC 230 of the present invention, in order to measure the DCO clock period Tv, one or two delay elements may be added to the number of delay elements corresponding to one period Tv of the DCO clock. That is, if there are 24 delay elements corresponding to the DCO clock period, a total of 48 delay elements are required when using the conventional TDC, but only 25 delay elements are required when using the TDC of the present invention.

Therefore, the TDC 230 of the present invention can reduce the number of delay elements required by about 50% compared to the conventional TDC 800, thereby significantly reducing the power consumption, noise, and area.

7 illustrates a detailed configuration of a digital loop filter, a lock detector, and a DCO according to an embodiment of the present invention.

Referring to FIG. 7, the digital loop filter 400 includes an IIR filter (hereinafter referred to as IIR) 410 for filtering the phase detector 300 and a digital low pass filter for determining the gain and PLL loop bandwidth of the loop filter. Hereinafter, a part of the 15-bit fractional word value (W _F ) of the phase detector 300 and the DLF) 420 are input to output a 3-bit digital value for controlling the fine adjustment capacitor bank of the DCO 600. Sigma-delta modulator (hereinafter, SDM) 430 and the like.

The lock detector 500 receives the output bits 8b, 8b, and 7b of the DLF 420 as inputs, and provides a lock indication signal for determining a lock in the core locking mode, the intermediate locking mode, and the fine locking mode of the PLL loop. LDc, LDm, LDf) are generated.

The DCO 600 adjusts an 8-bit coarse adjustment value LFc for controlling the coarse adjustment bank provided from the DLF 420 according to the lock indication signals LDc and LDm of the lock detector 500, and the intermediate adjustment. Switching the fine tuning bank of the DCO 600 provided from the multiplexer (hereinafter referred to as MUX) 610 and the DLF 420 to select and output one of the 8-bit intermediate adjustment values LFm for controlling the bank. Dynamic element matching and thermometer code blocks (D & T) 620, MUX 610, or the like, to dynamically match the fine-tuned capacitance values while converting the 7-bit fine-tuned values (LFf) into thermometer code values. According to the output value of the D & T 620, the output frequency of the DCO core 630 and the DCO core 630, which adjusts the oscillation frequency through one of the coarse adjustment bank, the intermediate adjustment bank, and the fine adjustment bank, is divided by two DCO clocks ( Output divider of 2-divider (hereinafter, DIV-2) 640 and DIV-2 640 to generate CKV) 4 divides the can may comprise a 4-min period (hereinafter, DIV-4) (650), including providing the SDM (430).

Hereinafter, the operation of the digital loop filter, the lock detector, and the DCO will be described.

The lock detector 500 receives each output bit (8 bits, 8 bits, 7 bits) of the DLF 420 of the digital loop filter 400 as an input to determine the lock in the core locking mode, the intermediate locking mode, and the fine locking mode of the PLL loop. The lock instruction signals LDc, LDm, and LDf are generated.

The core locking signal LDc is generated by receiving an 8-bit coarse adjustment value LFc from the DLF 420 and notifies whether the PLL loop is locked in the core locking mode of the PLL. The transition from the low state to the high state indicates that the Coarse PLL loop is locked. In this case, the MUX 610 freezes each bit of the coarse adjustment value LFc of the DLF 420 according to the core locking signal LDc, and the DCO core 630 copes the core of the DLF 420. The capacitance value of the coarse adjustment bank is controlled according to the adjustment value LFc to adjust the frequency of the DCO clock CKV.

The intermediate locking signal LDm is generated by receiving the 8-bit intermediate adjustment value LFm from the DLF 420 and notifies whether the PLL loop is locked in the intermediate locking mode of the PLL. The transition from the low state to the high state indicates that the intermediate PLL loop is locked. Then, the MUX 610 freezes each bit of the intermediate adjustment value LFm of the DLF 420 according to the intermediate locking signal LDm, and the DCO core 630 freezes the middle of the DLF 420. The frequency value of the DCO clock CKV is controlled by controlling the capacitance value of the intermediate adjustment bank according to the adjustment value LFm.

The fine locking signal LDf is generated by receiving the 7-bit fine adjustment value LFf from the DLF 420 and notifies whether the PLL loop is locked in the fine locking mode of the PLL. When the transition from the low state to the high state indicates that the fine PLL loop is locked. The fine locking signal LDf enters the input of the DLF 420 and changes the gain of the DLF 420 so that the finer phase error of the phase detector 300 can be tracked through the PLL loop.

The D & T 620 receives the 7-bit fine tuning value LFf from the DLF 420 and converts it into a thermometer code. The DCO core 630 turns on each capacitor of the fine tuning bank according to the converted thermometer code. Off-switching allows fine tuning of the frequency of the DCO clock (CKV).

On the other hand, the SDM 430 receives the upper 8-bit fractional word value from the 15-bit fractional word value of the DLF 420 to generate a 3-bit output, the DCO core 630 is 3 in the fine adjustment bank By switching the two microcapacitors on and off, the capacitance of the fine tuning bank is finely shaken to increase the resolution of the output frequency of the DCO core 630.

8 is a diagram illustrating a detailed configuration of a lock detector according to an embodiment of the present invention.

Referring to FIG. 8, the lock detector 500 compares bit values of the loop filter signals LF [m−1: 0] provided from the digital loop filter 400 with each other, thereby comparing the loop filter signal LF [ a comparator for outputting a signal CPo of one bit informing the time when each bit of m-1: 0]) is fixed and the time when all bits of the loop filter signal LF [m-1: 0] are fixed. After generating a plurality of delay signals having different phases from the output signal CPo of the comparator 510, the plurality of delay signals and the output signal CPo of the comparator 510 are generated. Delay cell block 520 for outputting an impulse-type clock signal DLout by logic OR (XOR), and a signal value change point of the output signal DLout of the delay cell block 520 are detected, and at this point DCO And a detector 530 for outputting the lock indication signal LD for switching the operation mode of the display device 600. At this time, the lock detector 500 receives an 8-bit coarse adjustment value LFc, an 8-bit intermediate adjustment value LFm, and a 7-bit fine adjustment value LFf from the digital loop filter 400, and performs a core locking signal. LDc, 8-bit intermediate locking signal LDm, and 7-bit fine locking signal LDf.

9 is a diagram illustrating a detailed configuration of a comparator, a delay cell block, and a detector according to an embodiment of the present invention.

Referring to FIG. 9, the comparator 510 has a plurality of delays in which the loop filter signal LF [m-1: 0] delays each bit by one period of the retimed clock CKRp or CKRn. 511, a plurality of comparators 512 for performing an XOR operation on the loop filter signals LF [m-1: 0] and the output signals of the plurality of delayers 511 bit by bit, and a plurality of comparators 512. And an operator 513 for outputting a 1-bit signal CPo by performing an OR operation on the output signal.

The delay cell block 520 is a delay chain 521 for delaying the output CPo of the comparator 510 by one period of the timed clock CKRp or CKRn, and the output of the comparator 510 ( And an operator 522 for outputting an impulse clock signal DLout by ORing the output of the CPo and the delay chain 521.

The detection unit 530 is configured to detect a latch circuit 531 for detecting a signal value change point of the output signal DLout of the delay cell block 520 and a lock instruction signal LD in response to an output of the latch circuit 531. ) May include a pulse generator 532 and the like.

Hereinafter, the operation of the lock detector of the present invention will be described with reference to FIGS. 10A to 10E. In this case, it is assumed that the lock detector of the present invention receives the loop filter signals LF [0] to LF [7] having the signal values as shown in FIG. 10A.

First, the comparison unit 510 cycles each bit of the loop filter signals LF [0] to LF [7] through one of the delayed clocks CKRp or CKRn through the plurality of delay units 511. Delays the signal, and performs an XOR operation for each bit with the loop filter signal LF [m-1: 0] through the plurality of comparators 512, as shown in FIG. 10B (CP [0] to CP [7). ]) And then OR operation through the calculator 513 to generate a signal CPo as shown in FIG. 10C.

When a predetermined time has elapsed and the all-digital PLL 100 is locked, the signal values of the loop filter signals LF [0] to LF [7] are kept constant, and thus the output signals of the plurality of delay units 511 The signal values of the loop filter signals LF [0] to LF [7] are also continuously changed, and are kept constant when a predetermined time is exceeded.

As a result, the output signals CP [0] to CP [7] of the plurality of comparators 512 are kept low when a predetermined time (for example, about 4.5 μsec) or more, as shown in FIG. 10B. When the output signal CPo of the calculator 513 also becomes longer than the predetermined time, the output signal CPo is kept low. Therefore, in the present invention, the time required for the lock of the all-digital PLL 100 can be calculated using the output signal CPo of the comparator 510.

Subsequently, the delay cell block 520 delays the phase of the output signal CPo of the comparator 510 little by little through the delay chain 521, and then compares the comparator 510 with the calculator 522. OR of both the output signal CPo and the output signals of the delay chain 521 are maintained in a high state before the fully digital PLL 100 is locked as shown in FIG. 10D, and the fully digital PLL 100 is locked. The clock signal DLout, which transitions to the low state, is output.

Then, the latch circuit 531 is synchronized with the falling edge of the clock signal DLout to generate a high level signal, and the pulse generator 532 responds to the lock instruction signal LD as shown in FIG. 10E. ).

That is, the lock detector of the present invention may include a delay circuit and a comparison circuit instead of a lookup table having a complicated structure using a memory as in the conventional lock detector, thereby performing a lock detection operation.

FIG. 11A illustrates a process of fixing an output frequency of a digital PLL according to an embodiment of the present invention. The output frequency of the digital PLL continuously changes with time, and is locked to a fixed value after a predetermined time. 11B shows the output frequency spectrum of the digital PLL according to the present embodiment, and it can be seen that it is locked while showing a loop bandwidth at 2.17 GHz.

12 is a diagram illustrating a detailed configuration of a timed clock generating unit according to an embodiment of the present invention.

Referring to FIG. 12, the timed clock generator 700 acquires and outputs a signal value of a reference clock FREF and a clock in synchronization with a rising edge of the DCO clock CKV. A second latch circuit 720 may be included in synchronization with the falling edge of the CKV to acquire and output a signal value of the reference clock FREF.

Accordingly, the retarded clock generator 700 has a lower frequency than the DCO clock CKV through the first latch circuit 710, but the rising edge timed clock CKRp synchronized to the rising edge of the DCO clock CKV. The second latch circuit 720 outputs the falling edge timed clock CKRn having a frequency lower than that of the DCO clock CKV but synchronized to the falling edge of the DCO clock CKV.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art.

100: fully digital PLL 200: phase counter
300: phase detector 400: digital loop filter
500: lock detector 600: DCO
700: timed clock generator 210: reference phase accumulator
220: variable phase accumulator 230: TDC
231: delay chain 232: sampler
233: edge detector 234: normalized multiplier
510: comparison unit 520: delay cell block
530: detection unit

Claims (19)

A phase counter for accumulating a phase set word value and a phase of a digital controlled oscillator (DCO) clock and detecting a fine phase difference between the reference clock and a timed clock;
A phase detector for detecting a digital phase error value by compensating for a phase difference between the frequency setting word and the DCO clock according to a fine phase difference between the reference clock and the retimed clock;
A digital loop filter for filtering the digital phase error value and controlling a PLL loop operating characteristic;
A lock detector detecting a time point at which the output of the digital loop filter is constant and generating a lock indication signal;
A digitally controlled oscillator in which a frequency of the DCO clock is changed according to an output of the digital loop filter while switching an operation mode according to the lock indication signal; And
And a timed clock generator for generating said timed clock which timed said DCO clock to a lower frequency.
The clock generator of claim 1, wherein the timed clock generator is
A first latch circuit synchronized with a rising edge of the DCO clock to obtain and output a signal value of the reference clock to generate a rising edge timed clock; And
And a second latch circuit synchronized with a falling edge of the DCO clock to acquire and output a signal value of the reference clock to generate a falling edge timed clock.
The method of claim 2, wherein the phase counter
A reference phase accumulator for accumulating a phase of the frequency setting word according to the rising edge timed clock;
A variable phase accumulator for accumulating a phase of the DCO clock;
A sampler for detecting a change amount of the DCO clock by sampling a value of the variable phase accumulator according to the rising edge timed clock; And
And a time to digital converter (TDC) for detecting a phase difference between the reference clock and the rising edge timed clock.
The method of claim 3, wherein the TDC is
A delay chain for delaying the phase of the reference clock;
A sampler sampling the output of the delay chain according to the rising edge timed clock and the falling edge timed clock, respectively;
An edge detector which detects a time point at which the output value of the sampler changes, and obtains a microphase difference between the reference clock and the rising edge timed clock and a microphase difference between the reference clock and the falling edge timed clock; And
A DCO clock period is calculated by subtracting and doubling the microphase difference between the reference clock and the rising edge timed clock and the microphase difference between the reference clock and the falling edge timed clock, and calculating the DCO clock period using the DCO clock period. And a normalized multiplier for normalizing and outputting a microphase difference between a clock and the rising edge timed clock.
5. The apparatus of claim 4, wherein the normalized multiplier
A subtractor for subtracting the microphase difference between the reference clock and the rising edge timed clock and the microphase difference between the reference clock and the falling edge timed clock;
An absolute value obtainer for obtaining an absolute value of the output of the subtractor;
A multiplier for obtaining the DCO clock period by doubling the output of the absolute value obtainer; And
And a multiplier for multiplying the fine phase difference between the reference clock and the rising edge timed clock by the reciprocal of the DCO clock period.
6. The system of claim 5 wherein the normalized multiplier
A DCO clock cycle averaging unit for averaging the DCO clock cycles obtained through the multiplier;
A multiplexer for selecting and outputting one of a DCO clock period obtained through the multiplier and a DCO clock period averaged through the DCO clock period averaging unit; And
And a memory for storing the selected DCO clock period through the multiplexer.
The method of claim 3, wherein the TDC is
A delay chain for delaying the phase of the reference clock;
A sampler sampling the output of the delay chain according to the rising edge timed clock;
An edge detector which detects a time point at which the output value of the sampler changes, and obtains a microphase difference between the reference clock and the rising edge timed clock; And
After obtaining the maximum value and the minimum value of the microphase difference between the reference clock and the rising edge timed clock, subtraction operation is performed to calculate the DCO clock period. And a normalized multiplier for normalizing and outputting the phase difference.
8. The system of claim 7, wherein the normalized multiplier
A maximum and minimum detector for detecting a maximum value and a minimum value of a microphase difference between the reference clock and the rising edge timed clock;
A subtractor for subtracting the maximum value and the minimum value to obtain the DCO clock period; And
And a multiplier for multiplying the fine phase difference between the reference clock and the rising edge timed clock by the reciprocal of the DCO clock period.
9. The apparatus of claim 8 wherein the normalized multiplier
A multiplexer for selecting and outputting one of a DCO clock period and a preset DCO clock period obtained through the subtractor; And
And a memory for providing the output of the multiplexer to the multiplier.
The method of claim 1, wherein the lock detector is
A comparison unit comparing the output of the digital loop filter bit by bit;
A delay cell block generating a plurality of delay signals having different phases from the output of the comparator, and logically combining the plurality of delay signals and the output of the comparator; And
And a detector which detects an output value change time point of the delay cell block and outputs the lock indication signal.
The method of claim 10, wherein the comparison unit
A plurality of delayers for phase-delaying the output of the digital loop filter bit by bit;
A plurality of comparators for bit-by-bit comparison between the output of the digital loop filter and the output of the plurality of delayers; And
And a calculator configured to perform an OR operation on the outputs of the plurality of comparators.
The method of claim 11, wherein the delay cell block is
A delay chain for delaying a phase of the output of the comparator; And
And an operator configured to perform an OR operation on the output of the delay chain and the output of the comparator.
The method of claim 10, wherein the detection unit
A latch circuit for detecting a time point at which an output value of the delay cell block changes; And
And a pulse generator for outputting a lock instruction signal in response to the output of the latch circuit.
The oscillator of claim 1, wherein the digitally controlled oscillator
Selecting one of a coarse adjustment bank, an intermediate adjustment bank, and a fine adjustment bank according to the lock indication signal, and varying the capacitance value of the selected adjustment bank according to the output of the digital loop filter to control the frequency of the DCO clock. Fully digital phase locked loop.
A delay chain for delaying the phase of the reference clock;
A sampler configured to receive a rising edge timed clock and a falling edge timed clock that synchronize the reference clock with rising and falling edges of the DCO clock, and sample the output of the delay chain;
An edge detector which detects a time point at which the output value of the sampler changes, and obtains a microphase difference between the reference clock and the rising edge timed clock and a microphase difference between the reference clock and the falling edge timed clock; And
A DCO clock period is calculated by subtracting and doubling the microphase difference between the reference clock and the rising edge timed clock and the microphase difference between the reference clock and the falling edge timed clock, and calculating the DCO clock period using the DCO clock period. TDC (Time to Digital Converter) for a fully digital phase-locked loop including a normalized multiplier for normalizing and outputting a microphase difference between a clock and the rising edge timed clock.
16. The apparatus of claim 15, wherein the normalized multiplier
A subtractor for subtracting the microphase difference between the reference clock and the rising edge timed clock and the microphase difference between the reference clock and the falling edge timed clock;
An absolute value obtainer for obtaining an absolute value of the output of the subtractor;
A multiplier for obtaining the DCO clock period by doubling the output of the absolute value obtainer; And
And a multiplier for multiplying the inverse of the DCO clock period by the microphase difference between the reference clock and the rising edge timed clock.
A delay chain for delaying the phase of the reference clock;
A sampler that receives a timed clock that synchronizes the reference clock to an output of a digitally controlled oscillator (DCO) and samples the output of the delay chain;
An edge detector which detects a time point at which the output value of the sampler changes, and obtains a microphase difference between the reference clock and the rising edge timed clock; And
After obtaining the maximum value and the minimum value of the microphase difference between the reference clock and the rising edge timed clock, subtraction operation is performed to calculate the DCO clock period. TDC (Time to Digital Converter) for a fully digital phase-locked loop that includes a normalized multiplier that normalizes and outputs the phase difference.
18. The apparatus of claim 17, wherein the normalized multiplier
A maximum and minimum detector for detecting a maximum value and a minimum value of a microphase difference between the reference clock and the rising edge timed clock;
A subtractor for subtracting the maximum value and the minimum value to obtain the DCO clock period; And
And a multiplier for multiplying the inverse of the DCO clock period by the microphase difference between the reference clock and the rising edge timed clock.
A comparator for receiving a plurality of bit signals from a digital loop filter and outputting one bit signal including information on whether each of the plurality of bit signals is locked;
A delay cell block outputting one clock signal by combining the one bit signal and the signal delaying the one bit signal by a predetermined time; And
And a detector for detecting a signal value change time point of the one clock signal and outputting a lock indication signal for switching an operation mode of the digitally controlled oscillator.

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