KR20230055101A - Phase locked loop and operation method thereof - Google Patents

Abstract

A phase-locked loop according to an embodiment of the present disclosure comprises: a voltage-controlled oscillator that generates an output clock signal; a divider that divides the output clock signal to generate a divided clock signal; a phase-frequency error detector that detects a first phase difference between a reference clock signal and the divided clock signal and outputs a first error signal corresponding to the first phase difference; a digital time converter that generates a delayed clock signal by delaying the phase of the reference clock signal; an oversampling phase detector that samples the delayed clock signal at a rising edge or falling edge of the output clock signal to generate an error indication signal to detect a second phase difference between the output clock signal and the delayed clock signal; and a voltage-to-current converter that outputs a second error signal corresponding to the second phase difference. According to an embodiment of the present disclosure, the power consumption, complexity, and area of the phase-locked loop can be reduced.

Description

Phase locked loop and its operation method {PHASE LOCKED LOOP AND OPERATION METHOD THEREOF}

The present disclosure relates to a phase-locked loop and an operating method thereof, and more particularly, to a fractional phase-locked loop incorporating an oversampling phase detector.

Recently, a charge pump phase locked loop (PLL) is mainly used to implement a radio frequency (RF) frequency synthesizer for multi-band mobile communication. However, analog circuit design technology is integrated in the charge pump phase-locked loop, and an additional analog RF library is required in addition to the design library provided by the standard digital CMOS process due to analog circuit and analog signal characteristics.

Charge-pump phase-locked loops are difficult to integrate with digital baseband signal processing blocks that use digital CMOS processes. Recently, digital RF PLLs have been researched and developed, but they reduce in-band noise and fractional spurs due to digital quantization noise. there was a limit to

Since the noise of the PLL frequency synthesizer directly affects the quality of wired and wireless communication, research to improve it is being actively conducted. Recently, in an attempt to reduce PLL in-band noise, many research results on an injection-locking PLL or a subsampling PLL have been published. In particular, a method of improving in-band noise of a charge pump PLL by using an oversampling method has been proposed.

The present disclosure provides a fractional phase-locked loop with a built-in oversampling phase detector for reducing phase-locked loop in-band noise by removing charge pump noise and an operating method thereof.

A phase-locked loop according to an embodiment of the present disclosure includes a voltage controlled oscillator for generating an output clock signal, a divider for generating a divided clock signal by dividing the output clock signal, and a first phase between a reference clock signal and the divided clock signal. A phase-frequency error detector detecting a difference and outputting a first error signal corresponding to the first phase difference, a digital time converter generating a delayed clock signal by delaying the phase of the reference clock signal, the output clock signal, and an oversampling phase detector configured to generate an error indication signal by sampling the delayed clock signal at a rising edge or a falling edge of the output clock signal to detect a second phase difference between the delayed clock signals, and the second phase difference and a voltage-to-current converter outputting a second error signal corresponding to .

A method of operating a phase-locked loop according to an embodiment of the present disclosure includes generating a divided clock signal by dividing an output clock signal, detecting a first phase difference between a reference clock signal and the divided clock signal, and determining the first phase outputting a first error signal corresponding to the difference, generating a delayed clock signal by delaying the phase of the reference clock signal, detecting a second phase difference between the output clock signal and the delayed clock signal, Generating an error indication signal by sampling the delayed clock signal at a rising edge or a falling edge of the output clock signal, and outputting a second error signal corresponding to the second phase difference.

According to an embodiment of the present disclosure, power consumption, complexity, and area of a phase locked loop may be reduced, and phase noise may be reduced.

1 shows a configuration of a phase locked loop according to an embodiment of the present disclosure.
FIG. 2A shows an example of output characteristics of a first error signal output from the phase-frequency error detector of FIG. 1 .
FIG. 2B shows an example of output characteristics of a second error signal output from the voltage-to-current converter of FIG. 1 .
3 is a flowchart illustrating a method of operating a phase locked loop according to an embodiment of the present disclosure.
4 illustrates phase noise of a simulated VCO clock when an oversampling phase detector of a phase locked loop is not operated (ie, turned off) according to an embodiment of the present disclosure.
5 illustrates phase noise of a simulated VCO clock when an oversampling phase detector of a phase locked loop is operated (ie, turned on) according to an embodiment of the present disclosure.

In the following, embodiments of the present disclosure will be described clearly and in detail so that those skilled in the art can easily practice the present disclosure.

Components described with reference to terms such as unit, unit, module, block, ~or, ~er, etc. used in the detailed description and functional blocks shown in the drawings are It may be implemented in the form of software, hardware, or a combination thereof. Illustratively, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, integrated circuit cores, a pressure sensor, an inertial sensor, a microelectromechanical system (MEMS), a passive component, or a combination thereof. .

1 shows a configuration of a phase locked loop 100 according to an embodiment of the present disclosure. The phase locked loop 100 includes a modulator 110, a divider 120, a phase-frequency error detector 130, a digital time converter 140, an oversampling phase detector 150, a voltage-to-current converter 160, It may include a summer 170, a filter 180, and a voltage controlled oscillator (VCO) 190.

The phase locked loop 100 may constantly fix the frequency of the output clock signal CLK_OUT in response to the reference clock signal CLK_REF generated from the reference clock generator 10 . For example, the phase locked loop 100 may fix the frequency of the output clock signal CLK_OUT to a constant value by compensating for a phase difference between the output clock signal CLK_OUT and the reference clock signal CLK_REF.

The modulator 110 may accumulate a frequency command word (FCW), and may output the accumulated value to the divider 120 and the digital time converter 140. For example, the modulator 110 may be a sigma-delta modulator, but the present disclosure is not limited thereto.

The divider 120 divides the output clock signal CLK_OUT received from the VCO 190 based on the accumulated value of the frequency setting word FCW output from the modulator 110 to generate the divided clock signal CLK_DIV. can do. Specifically, the divider 120 may divide the output clock signal CLK_OUT by 1 or N, which is an integer greater than 1, to precisely control the reference clock signal CLK_REF and output the divided clock signal CLK_DIV. For example, the divided clock signal CLK_DIV may be generated to have a frequency different from that of the reference clock signal CLK_REF. The divider 120 may transmit the divided clock signal CLK_DIV to the phase-frequency error detector 130 .

The phase-frequency error detector 130 may detect a frequency difference or a phase difference between the reference clock signal CLK_REF and the divided clock signal CLK_DIV, and obtain a first error signal E1 corresponding to the detected frequency difference or phase difference. ) can be output. For example, the first error signal E1 may be a current signal that changes according to a phase difference. An example of output characteristics of the first error signal E1 is described with reference to FIG. 2A.

The digital time converter 140 may generate a delayed clock signal CLK_DTC by delaying the phase of the reference clock signal CLK_REF based on the accumulated value of the frequency setting word FCW output from the modulator 110, It can be transmitted to the oversampling phase detector 150.

The oversampling phase detector 150 may receive the delayed clock signal CLK_DTC and the output clock signal CLK_OUT, and samples the delayed clock signal CLK_DTC at a rising edge or a falling edge of the output clock signal CLK_OUT to generate an error. An indication signal Ve may be generated.

The oversampling phase detector 150 can detect a fractional phase difference between the output clock signal CLK_OUT and the delayed clock signal CLK_DTC, and the error indication signal Ve corresponding to the phase difference is an up signal ( UP) and down signals (DN). For example, when the phase of the output clock signal CLK_OUT is ahead of the phase of the delayed clock signal CLK_DTC, the oversampling phase detector 150 detects an up signal UP that is logic low and a down signal DN that is logic high. can output Conversely, when the phase of the output clock signal CLK_OUT lags behind the phase of the delayed clock signal CLK_DTC, the oversampling phase detector 150 outputs an up signal UP that is logic high and a down signal DN that is logic low. can do.

In addition, the oversampling phase detector 150 generates an early signal EARLY and a rate signal LATE indicating which of each phase of the delayed clock signal CLK_DTC and the output clock signal CLK_OUT is leading or lagging. can For example, while the delayed clock signal CLK_DTC precedes the output clock signal CLK_OUT, the oversampling phase detector 150 may output an early signal EARLY that is logic high and a rate signal LATE that is logic low, This may continue until the output clock signal CLK_OUT leads the reference clock signal CLK_REF.

When the output clock signal CLK_OUT precedes the delayed clock signal CLK_DTC, the oversampling phase detector 150 may output an early signal EARLY that is logic low and a rate signal LATE that is logic high. The oversampling phase detector 150 may transmit the error indication signal Ve, the early signal EARLY, and the rate signal LATE to the voltage-to-current converter 160 .

The voltage-to-current converter 160 generates a second error signal E2 corresponding to the up signal UP and the down signal DN based on the error indication signal Ve, the early signal EARLY, and the late signal LATE. ) can be output. Since the up signal UP and the down signal DN correspond to a minute phase difference between the delayed clock signal CLK_DTC and the output clock signal CLK_OUT, the second error signal E2 may indicate the phase difference. For example, the second error signal E2 may be a current signal that changes according to a phase difference. An example of output characteristics of the second error signal E2 is described with reference to FIG. 2B.

The summer 170 adds the first error signal E1 output from the phase-frequency error detector 130 and the second error signal E2 output from the voltage-current converter 160 to the filter 180. can transmit

The filter 180 may convert the sum of the first error signal E1 and the second error signal E2 output from the summer 170 into a control voltage VC, and output the voltage controlled oscillator 190. can do. For example, the filter 180 may operate as a low pass filter that removes a high frequency component from the sum of the first error signal E1 and the second error signal E2. For example, the filter 180 may include at least one capacitor and at least one resistor. However, the present disclosure is not limited thereto, and the filter 180 may be implemented in various configurations for removing a specific frequency component from the sum of the first error signal E1 and the second error signal E2.

The voltage controlled oscillator 190 may generate an output clock signal CLK_OUT by receiving the control voltage VC, and may output the output clock signal CLK_OUT to the divider 120 and the oversampling phase detector 150. The frequency and phase of the output clock signal CLK_OUT may vary depending on the characteristics of the system in which the phase locked loop 100 is installed.

FIG. 2A shows an example of output characteristics of the first error signal E1 output from the phase-frequency error detector 130 of FIG. 1 . 2A, the horizontal axis represents the phase difference Φ1 between the reference clock signal CLK_REF and the divided clock signal CLK_DIV, and the vertical axis represents the magnitude of the current I of the first error signal E1. Hereinafter, description will be made with reference to FIG. 1 together with FIG. 2A.

The first error signal E1 may be a signal corresponding to a phase difference Φ1 between the reference clock signal CLK_REF and the divided clock signal CLK_DIV detected by the phase-frequency error detector 130 . The phase-frequency error detector 130 may output the current I according to the phase difference Φ1 between the reference clock signal CLK_REF and the divided clock signal CLK_DIV as the first error signal E1. The magnitude of the current I may be proportional to the phase difference Φ1 between the reference clock signal CLK_REF and the divided clock signal CLK_DIV.

As shown in FIG. 2A, the slope of the straight line formed by the phase difference Φ1 and the current I is within the first range (-p1< It may be larger when the second range (p1<Φ1<p2, -p2<Φ1<-p1) than when Φ1<p1).

The slope of the straight line formed by the phase difference (Φ1) and the current (I) can represent the change in the size of the output current (I) according to the phase difference (Φ1), and the larger the slope of the straight line, the more the change in the phase difference (Φ1). It could mean better detection. In other words, the phase-frequency error detector 130 has a phase difference (Φ1) in the second range (p1<Φ1<p2, -p2<Φ1<-p1) than when the phase difference (Φ1) is in the first range (-p1<Φ1<p1). When , the change in the phase difference Φ 1 can be better detected.

FIG. 2B shows an example of output characteristics of the second error signal E2 output from the voltage-to-current converter 160 of FIG. 1 . 2B, the horizontal axis represents the phase difference Φ2 between the reference clock signal CLK_REF and the output clock signal CLK_OUT, and the vertical axis represents the magnitude of the current I of the second error signal E2. Hereinafter, a description will be made with reference to FIG. 1 together with FIG. 2B.

The second error signal E2 may be a signal corresponding to a phase difference Φ2 between the delayed clock signal CLK_DTC and the output clock signal CLK_OUT detected by the oversampling phase detector 150 . The oversampling phase detector 150 may output the current I according to the phase difference Φ2 between the delayed clock signal CLK_DTC and the output clock signal CLK_OUT as the second error signal E2. The magnitude of the current I may be proportional to the phase difference Φ2 between the delay clock signal CLK_DTC and the output clock signal CLK_OUT.

Similar to the description with reference to FIG. 2A, the slope of the straight line formed by the phase difference Φ2 and the current I is within the second range ( It may be larger when the first range (-p1<Φ2<p1) than when p1<Φ2<p2, -p2<Φ2<-p1).

The slope of the straight line formed by the phase difference (Φ2) and the current (I) can represent the change in the size of the output current (I) according to the phase difference (Φ2), and the larger the slope of the straight line, the more the change in the phase difference (Φ2). It could mean better detection. In other words, the oversampling phase detector 150 has the phase difference Φ2 in the first range (-p1<Φ2<p1) rather than the second range (p1<Φ2<p2, -p2<Φ2<-p1). The change in the phase difference (Φ2) can be better detected when

Referring to FIGS. 2A and 2B together, the phase difference Φ2 between the reference clock signal CLK_REF and the frequency division clock signal CLK_DIV and the phase between the output clock signal CLK_OUT and the delay clock signal CLK_DTC Both the difference Φ2 may indicate a phase difference between the reference clock signal CLK_REF and the output clock signal CLK_OUT. For convenience of explanation below, it is assumed that the phase difference Φ1 and the phase difference Φ2 represent the phase difference Φ between the reference clock signal CLK_REF and the output clock signal CLK_OUT.

When the phase difference Φ is in the first range (-p1<Φ<p1), the oversampling phase detector 150 further detects a change in the phase difference Φ between the reference clock signal CLK_REF and the output clock signal CLK_OUT. It can be detected well, and the effect of the phase-frequency error detector 130 on detecting the phase difference (Φ) change (ie, the effect on phase locking) can be reduced.

On the other hand, when the phase difference Φ is in the second range (p1<Φ<p2, -p2<Φ<-p1), the phase-frequency error detector 130 outputs the reference clock signal CLK_REF and the output clock signal CLK_OUT. It is possible to better detect the change in the phase difference (Φ) between the two phases, and relatively the effect of the oversampling phase detector 150 on the detection of the change in the phase difference (Φ) (that is, the effect on phase locking) can be reduced.

3 is a flowchart illustrating an operating method of the phase locked loop 100 according to an embodiment of the present disclosure. Hereinafter, it will be described with reference to FIG. 1 together with FIG. 3 .

In step S110, the phase-frequency error detector 130 may detect a frequency difference or a phase difference between the reference clock signal CLK_REF and the divided clock signal CLK_DIV and output a first error signal E1. The divided clock signal CLK_DIV may be a signal obtained by dividing the output clock signal CLK_OUT by 1 or N, which is an integer greater than 1, from the divider 120 to precisely control the reference clock signal CLK_REF. For example, the divided clock signal CLK_DIV may be generated to have a frequency different from that of the reference clock signal CLK_REF.

In step S120, the digital time converter 140 generates a delayed clock signal CLK_DTC by delaying the phase of the reference clock signal CLK_REF based on the accumulated value of the frequency setting word FCW output from the modulator 110. can

In step S130 , the oversampling phase detector 150 may generate an error indication signal Ve by sampling the delayed clock signal CLK_DTC at a rising edge or a falling edge of the output clock signal CLK_OUT. In step S140, the oversampling phase detector 150 generates an error indication signal Ve, an early signal EARLY, and a rate signal LATE according to a minute phase difference between the output clock signal CLK_OUT and the delayed clock signal CLK_DTC. ) can be output. As described with reference to FIG. 1 , the error indication signal Ve may correspond to the up signal UP and the down signal DN, and the early signal EARLY and the rate signal LATE correspond to the reference clock signal CLK_REF ) and the output clock signal CLK_OUT may be a pulse signal indicating which one is ahead.

In step S150, the voltage-to-current converter 160 generates a second signal corresponding to the up signal UP and the down signal DN based on the error indication signal Ve, the early signal EARLY, and the rate signal LATE. An error signal E2 can be output. In step S160, the filter 180 filters the sum of the first error signal E1 and the second error signal E2, converts the sum of the first error signal E1 and the second error signal E2 into a control voltage VC, and outputs the output clock signal CLK_OUT to the voltage control oscillator 190. ) can be created.

4 shows phase noise of a simulated VCO clock when the oversampling phase detector 150 of the phase locked loop is not operated (ie, turned off) according to an embodiment of the present disclosure. Referring to the simulation results shown in FIG. 4, the in-band noise is about -68dBc/Hz.

5 shows phase noise of a simulated VCO clock when the oversampling phase detector 150 of the phase locked loop is operated (ie, turned on) according to an embodiment of the present disclosure. Referring to the simulation results shown in FIG. 5, the in-band noise is about -95dBc/Hz.

Referring to FIGS. 4 and 5, which are simulation results, the frequency of the VCO clock is 19.851 GHz, and when the oversampling phase detector 150 is operated (ie, turned on), in-band noise is improved by about 25 dB. can confirm that Therefore, it can be seen that the oversampling phase detector 150 according to an embodiment of the present disclosure can effectively suppress in-band noise.

The foregoing are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments and should be defined by not only the claims to be described later but also those equivalent to the claims of the present invention.

100: phase locked loop
110 modulator
120: divider
130: phase-frequency error detector
140: digital time converter
150: oversampling phase detector
160: voltage-to-current converter
170: totalizer
180: filter
190: voltage controlled oscillator

Claims (10)

a voltage controlled oscillator generating an output clock signal;
a frequency divider generating a divided clock signal by dividing the output clock signal;
a phase-frequency error detector that detects a first phase difference between a reference clock signal and the frequency division clock signal and outputs a first error signal corresponding to the first phase difference;
a digital time converter generating a delayed clock signal by delaying a phase of the reference clock signal;
an oversampling phase detector configured to generate an error indication signal by sampling the delayed clock signal at a rising edge or a falling edge of the output clock signal to detect a second phase difference between the output clock signal and the delayed clock signal; and
and a voltage-to-current converter outputting a second error signal corresponding to the second phase difference. According to claim 1,
The error indication signal may correspond to an up signal and a down signal indicating the second phase difference,
when the phase of the delayed clock signal precedes the phase of the output clock signal, the up signal has a logic high value and the down signal has a logic low value; and
When the phase of the delayed clock signal lags behind the phase of the output clock signal, the up signal has a logic low value and the down signal has a logic high value. According to claim 2,
the oversampling phase detector generates an early signal and a rate signal indicating which of the up signal and the down signal is leading;
the early signal has a logic high value and the rate signal has a logic low value while the delayed clock signal precedes the output clock signal; and
The early signal has a logic low value and the rate signal has a logic high value while the up signal lags behind the output clock signal. According to claim 3,
The voltage-to-current converter outputs the second error signal based on the error indication signal, the early signal, and the rate signal. According to claim 1,
A high frequency component is removed from the sum of the first error signal and the second error signal, a control voltage is generated based on the first error signal and the second error signal, and the control voltage is output to the voltage control oscillator. Including a filter that
The voltage-controlled oscillator is controlled based on the control voltage. generating a divided clock signal by dividing the output clock signal;
detecting a first phase difference between a reference clock signal and the frequency division clock signal, and outputting a first error signal corresponding to the first phase difference;
generating a delayed clock signal by delaying a phase of the reference clock signal;
generating an error indication signal by sampling the delayed clock signal at a rising edge or a falling edge of the output clock signal to detect a second phase difference between the output clock signal and the delayed clock signal; and
and outputting a second error signal corresponding to the second phase difference. According to claim 6,
and removing a high frequency component from the sum of the first error signal and the second error signal, and converting the signal from which the high frequency component has been removed into a control voltage. According to claim 6,
The error indication signal may correspond to an up signal and a down signal indicating the second phase difference,
When the phase of the oversampling clock signal precedes the phase of the delayed clock signal, the up signal has a logic high value and the down signal has a logic low value;
When the phase of the oversampling clock signal lags behind the phase of the delayed clock signal, the up signal has a logic low value and the down signal has a logic high value. According to claim 8,
The step of outputting the second error signal indicates which signal of the delay signal and the oversampling clock signal is leading, or an early signal and rate indicating which of the delay signal and the output clock signal is leading Further comprising generating a signal,
the early signal has a logic high value and the rate signal has a logic low value while the delay signal precedes the oversampling clock signal; and
The early signal has a logic low value and the rate signal has a logic high value while the delay signal lags behind the oversampling clock signal. According to claim 9,
The outputting of the second error signal further comprises generating the second error signal based on the error indication signal, the early signal, and the rate signal.

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