JP2000241524A - Digital processing pll - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a standard signal oscillator by which the time until a signal is synchronized is short while the influence of an SA is being removed, which has a frequency stability equal to that of a cesium oscillator, which is low-cost and whose maintenance operation is small. SOLUTION: In this digital processing PLL, the output signal of a voltage- controlled oscillator(VCO) 7 is compared with a reference output signal from a GPS, and the VCO 7 is controlled by using a PLL control part 3 so that both phases agree. The digital processing PLL is featured in such a way that the PLL control part 3 is provided with a high-speed leading-in control means 22 which obtains a VCO control voltage used to generate a frequency as a target while an amount by which the VCO control voltage is changed until a prescribed time elapses from the start of a control operation is compared with control voltage-frequency characteristic data measured by the VCO individually in advance so as to be computed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital processing PLL for controlling an oscillation frequency of a voltage controlled oscillator.
For more information on (Phase Locked Loop: Phase Locked Loop), more specifically, a voltage controlled crystal oscillator (VCXO)
Is compared with the phase of a reference input signal from a GPS (Global Positioning System), and the VCXO is controlled using a PLL control unit so that the phases of both signals match. And a digital processing PLL for performing the following.

[0002]

2. Description of the Related Art In recent years, with the advancement of a highly information-oriented society, the accuracy required for a reference frequency in an information communication network has been increased. In particular, digital wire communication networks and mobile communication networks require high accuracy in reference frequencies. At present, in a communication system requiring high-accuracy network synchronization, a cesium oscillator (atomic frequency standard signal oscillator) is used as a standard oscillator. However, the cesium oscillator has a problem that it is expensive and requires regular adjustment and maintenance work. In a communication system in which a cesium oscillator is used as a master oscillator and a reference frequency is generated and distributed using a highly stable crystal oscillator as a slave oscillator, the frequency accuracy of the slave oscillator becomes insufficient as the frequency increases due to an increase in the amount of information. There is a problem. This is because, for example, in a conventional communication system, a buffer memory for data is installed in order to cope with a frequency synchronization deviation. Due to the very large amount of buffer memory required. Also,
When information is transmitted at high speed and in large quantities due to the increase in communication frequency, temporarily storing data in the buffer memory itself may hinder high-speed communication. There is a need for a system. Therefore, in a slave oscillator of a communication system using a high frequency, a buffer memory is not required by using a rubidium atomic frequency standard signal oscillator which is relatively inexpensive as compared with a cesium oscillator. But,
Rubidium atomic frequency standard signal oscillators are also more expensive than crystal oscillators, and require regular maintenance, such as replacing lamps and gas cells every few years, to maintain accuracy. Have a problem. Therefore, in order to realize an inexpensive communication system, a standard oscillator using a GPS timing signal as a reference signal has been used. That is, the output signal of the voltage controlled crystal oscillator (VCXO) is compared with the timing signal supplied from the GPS, and the VCXO is controlled so that the phase difference between the two becomes zero.
A standard signal is obtained by using a phase locked loop (PLL) for controlling the XO.

[0003] A digital processing PLL (DPPL) will be described below as an example of a conventional PLL standard oscillator.
A standard oscillator using L) will be described. FIG.
FIG. 2 is a configuration block diagram of a standard oscillator when a DPPLL is used. In FIG. 4, a phase comparator 1 has a phase of a reference input signal, which is a GPS timing signal input from one input terminal, and a phase of an output signal of a frequency divider 9 described later input from the other input terminal. And outputs a signal corresponding to the amount of phase difference between the two. The PLL control unit 3 generates a control signal in accordance with a signal indicating the amount of phase difference from the phase comparator 1. The phase of a signal obtained by dividing the output signal of the VCXO 7 described later is used as a reference input from the GPS. The control signal of the VCXO 7 is output as a digital signal so as to approach the phase of the signal. D / A (digital / analog) converter 5
Then, the digital control signal output from the PLL control unit 3 is converted into an analog control voltage Vcont and output.
The VCXO 7 is a crystal oscillator that oscillates at an oscillation frequency according to the control voltage Vcont, and a part of the output frequency is sent to a frequency divider 9 described later. The frequency divider 9 divides the output signal of the VCXO 7 at a predetermined frequency division ratio and outputs the resultant signal to the phase comparator 1. The operation of the standard oscillator shown in FIG. 4 will be described below. 1 received from GPS satellite
The GPS timing signal every second is input to one input terminal of the phase comparator 1 as a reference input signal. Phase comparator 1
Compares the output signal of the frequency divider 9 input from the other input terminal with the phase of the reference input signal, generates a signal corresponding to the phase difference between the two, and outputs the signal to the PLL control unit 3. The PLL control unit 3 generates a digital signal for controlling the VCXO 7 from the input signal and outputs the digital signal to the D / A converter 5.
The D / A converter 5 converts a digital signal into an analog control voltage Vcont and outputs it. VCXO7 has a frequency (for example, 5) corresponding to the input control voltage Vcont.
MHz) is supplied to an external circuit and a part thereof is output to the frequency divider 9. The frequency divider 9 divides the frequency input from the VCXO 7 (for example, 1/50000000 for a frequency of 5 MHz) and outputs it to the other input terminal of the phase comparator 1 as a signal of 1 Hz (one cycle per second). . Hereinafter, the above operation is repeated. By repeating this operation, the GPS timing signal and the output of the VCXO 7 are gradually synchronized.

FIG. 5 is a block diagram showing the inside of the PLL control section 3 in FIG. 4 in more detail. The PLL control unit 3 of FIG. 5 includes a switch 11 that performs a switching operation every one second generated inside the standard oscillator, a first averaging processing unit 12 that averages and outputs an input signal, and a first Integral operation section 1 for integrating the output averaged by averaging section 12
3, the output of the first averaging unit 12 and the integral operation unit 13
And a multiplication unit 15 for multiplying the output of the addition unit 14 by the sensitivity constant A of the crystal resonator.
And The integral operation unit 13, the addition unit 14, and the multiplication unit 15 form a complete integration type loop filter (low-pass filter in terms of characteristics) 16, which has a large gain for DC components. ing. The frequency characteristics (cutoff frequency and the like) of the loop filter 16 can be changed by each of the sensitivity constant A and the integration constant B of the crystal resonator. The sensitivity constant A (proportionality constant) of the crystal is D / D for controlling the frequency variable range of the VCXO 7 when the output of the loop filter 16 is 1 bit.
This is a coefficient for determining the number of bits to be input to the A converter 5. The integration constant B is the loop filter 1
6 is a coefficient for determining the frequency of the noise to be removed. The operation of the PLL control unit 3 shown in FIG. 5 will be described below. The signal from the phase comparator 1 becomes a signal every one second generated internally by the switch 11 and is input to the first averaging unit 12. The first averaging unit 12 calculates the phase difference from the phase comparator 1 by 10 to suppress white noise and cancel the sampling error.
It is averaged for seconds and output to the loop filter 16. The loop filter 16 performs an appropriate proportional operation and an integral operation on the input signal, and outputs a digital signal for controlling the VCXO 7. By using the above-described PLL control, the output of the phase difference amount from the phase comparator 1 becomes a gradually small value, and the same oscillation accuracy as that of the GPS timing signal can be obtained.

[0005]

However, as is well known, the GPS timing signal includes SA (selective signal).
(Availability), the frequency accuracy of a standard oscillator that obtains a standard signal by a PLL using a GPS timing signal as a reference signal is degraded as compared with a standard oscillator that uses a cesium oscillator as a reference signal. . Note that SA is an intentional phase shift superimposed on a GPS timing signal, and a dedicated (military) receiver uses this SA to reduce synchronization shift and improve positioning accuracy. This has the effect of increasing the frequency stability, but when the signal is received by a general-purpose receiver, the frequency stability is rather lowered. SA is a phase change that is slow, with one cycle being several tens of hours. In the conventional DPPLL, the frequency is synchronized as the phase difference between the input and the output approaches 0,
DPPLL (loop filter 1) for suppressing SA
When the proportional constant and integral constant of 6) are set, 1p
It takes a very long time to synchronize with ps (pulses / second). FIG. 6 is a graph comparing the frequency response (b) until the frequency converges to the target frequency with the conventional DPPLL and the phase response (a) until the phase difference disappears. In the phase response graph of a), the phase difference can be regarded as 0 when it is 1430 (Ksec) or more (1430 × 1000 (seconds) ≒ 16.55).
Day). Therefore, when trying to obtain the target frequency by suppressing the SA by the conventional DPPLL, about 16.
It will take 55 days. As described above, the standard oscillator that obtains the standard signal by the DPPLL using the GPS timing signal as the reference signal has a problem that a very long time is required to obtain the accuracy equivalent to the cesium oscillator. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem in a DPPLL using a timing signal supplied from a GPS as a reference signal, and has a short time until synchronization while eliminating the influence of SA and a cesium oscillator. It is an object of the present invention to provide an inexpensive standard signal oscillator having the same frequency stability and requiring less maintenance work.

[0006]

According to a first aspect of the present invention, there is provided a digital processing PLL comprising: an output signal of a voltage controlled oscillator (VCO);
The VCO is compared with a reference input signal from the S, and the VCO is controlled using a PLL control unit so that both phases match, and the influence of selective availability is removed using a complete integration type loop filter. In the digital processing PLL, the PLL control unit calculates an amount of change in the VCO control voltage from the start of the control until a predetermined time elapses by comparing the amount of change in the VCO control voltage with control voltage-frequency characteristic data measured individually for each VCO in advance. A high-speed pull-in control means for obtaining a VCO control voltage for generating a target frequency. According to a second aspect of the present invention, in the digital processing PLL according to the first aspect, the amount of change in the VCO control voltage is obtained by averaging a control signal of a D / A converter that generates a signal to be input to the VCO. It is characterized by. According to a third aspect of the present invention, in the digital processing PLL according to the first or second aspect, when the high-speed pull-in control unit obtains a VCO control voltage for generating a target frequency, Is characterized in that the integral value in is set to 0.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. When comparing the phase response graph of FIG. 6A with the frequency response graph of FIG. 6B, the frequency deviation becomes 0 at the time when the first peak point of the phase response appears.
It has become. Also, the phase response is
Changes according to the control value output from the controller. According to the present invention, based on the above, the characteristic reaching the first peak point of the phase response is detected in advance for each VCXO7, including the relationship with the control value, and the characteristic until the first peak point of the phase response appears appears. , The first peak point of the phase response is predicted, and the control value at the predicted peak point is calculated by the PLL control unit 3 as D
Output to the A / A converter 5, at which time the integration value of the integration operation unit 13 is set to 0, and the PLL operation is started again.
A standard signal oscillator having a frequency stability equivalent to that of a cesium oscillator is obtained while obtaining the synchronization state earlier than the conventional method and eliminating the influence of SA. FIG. 1 is a block diagram showing a configuration of a standard signal oscillator according to one embodiment of the present invention. Note that the same configuration as that used in FIG. 5 showing the prior art is denoted by the same reference numeral in FIG. 1 as in FIG. 5 and the description is omitted. The second averaging section 19 in FIG. 1 constitutes the high-speed pull-in control section 22, and averages and outputs the control value of the D / A converter 5 output from the loop filter 16. The frequency offset control unit 20
High-speed pull-in controller 2 together with second averaging device 19
2, the characteristic of each VCXO 7 reaching the first peak point of the phase response is detected in advance in correspondence with the change of the control value, and stored as, for example, control value data in a table format. The frequency offset means 20 detects the characteristic data until the first peak point in the phase response appears due to the change in the control value, and compares the data in which the control value has changed with the control value data in a table format stored in advance. By predicting the peak point
The control value at the peak point of the phase response is calculated. Then, a difference between the control value and the control value output from the loop filter 16 is output. The second adder 21 supplies the D / A converter 5 with the sum of the control value output from the loop filter 16 and the control value output from the frequency offset control unit 20, that is, the control value at the peak point of the phase response. Output.
Here, a method of setting a predicted value in the frequency offset control unit 20 will be described. For example, FIG. 2 shows that the frequency deviation between the reference input signal and the output signal of the frequency divider 9 is 1 × 10 −
9 is a diagram showing a control value (the number of control bits) output from the loop filter 16 at 9 and a value obtained by averaging the number of control bits by a second averaging processing device 19. FIG. It is assumed that only the output signal of the loop filter 16 is supplied to the D / A converter 5 in FIG. As shown in FIG.
^The D / A converter 5 calculates the frequency deviation of ^-9 as (1 × 10 ^-9 ) /
(6 × 10 ⁻¹³ ) ≒ It is set to be controlled by the number of control bits of 1638 (bits). Note that 6 × 10 ⁻¹³ in this equation is the oscillation frequency of the VCXO 7 that can be controlled per 1 control bit number of the D / A converter 5.
In this example, the average value of the number of D / A control bits one day after the start of the processing is 864, and the frequency deviation ΔF at this time is 1.67 × 10 ⁻¹⁰ (278 bits in number of bits). . Here, 864 (average value of control bits) /
A constant 3.1 for prediction is obtained from the equation of 278 (frequency deviation) ≒ 3.1. That is, by previously obtaining this constant, if the average value of the control bits is divided by the constant, the frequency deviation at that time can be estimated.

Next, an operation of canceling the influence of the frequency deviation and synchronizing at a high speed in this embodiment will be described. Since the control value output from the loop filter 16 includes a variation in SA that could not be suppressed by the complete integration type loop filter 16, the second averaging unit 19
Averages and outputs the control value of the D / A converter 5 output from the loop filter 16 in order to remove the variation remaining in the control value. The frequency offset control unit 20 obtains the number of control bits (278 bits) corresponding to the frequency deviation ΔF by dividing the average value (864 bits) of the number of control bits on the first day in FIG. 2 by 3.1,
The number of control bits corresponding to the obtained frequency deviation ΔF (278
) And the number of control bits (1360 bits) of the D / A converter 5 and outputs the result to the second adder 21. The second adder 21 outputs the added control bit. In this way, the number of control bits output to the D / A converter 5 can be set so that the frequency deviation becomes “0”. As described above, even if the time until the number of D / A control bits with a frequency deviation of “0” can be output can be reduced, the integration operation unit 1 in the loop filter 16
Since the integrated value remains in 3, a time is required from the peak point of the phase response until the phase response becomes “0”. In order to reduce this time, the integral value remaining in the integral operation unit 13 is reset to “0”, and the operation of the PLL control unit 3 is started again. In this manner, the standard signal oscillator according to the present embodiment eliminates the influence of SA and outputs a control value having a frequency deviation of “0” by calculation using the averaging result of the averaging processing unit 19 for one day. Therefore, the frequency deviation can be set to “0” faster than the conventional method of waiting for convergence by the PLL circuit. At this time, the integral value remaining in the integral operation unit 13 is temporarily set to “0”, and the PLL control unit 3 is started again, so that the phase response becomes “0” from the peak point of the phase response.
Can be shortened.

According to an experiment conducted by the inventor of the present invention to verify the above-described embodiment, the frequency characteristic of the SA superimposed on the actual GPS signal includes a phase change of one to two days. Therefore, the fluctuation amount was about ± 300 nsec at the maximum. FIG. 4 shows data obtained by recording the phase fluctuation of the actual SA input signal to the PLL control unit 3 and the phase fluctuation of the output signal of the VCXO 7 in which the SA is suppressed using the PLL control unit 3 of the present embodiment for one month. 3 is shown. FIG.
In the above, the phase variation of the reference input signal supplied from the GPS is about ± 300 nsec at maximum as described above, but the maximum phase variation in the output signal of the VCXO 7 is ± 300 nsec.
It is within about 50 nsec. Therefore, VCX in which SA is suppressed using the PLL control unit 3 of the present embodiment
It can be determined that the output signal of O7 has obtained sufficient characteristics as a standard signal oscillator. The VC used in the present embodiment
The stability of XO7 was 10 seconds (10S), and the drift amount was about 3 × 10 ^-13, a value comparable to that of a cesium oscillator. The cost of the oscillator used in this embodiment is G
It was about 1/4 of the cesium oscillator even if the PS receiver was included. According to the present invention, by providing the PLL control unit 3 with the high-speed pull-in control unit 22 as described above, it is possible to synchronize the frequency at high speed while eliminating the influence of SA and obtain the output of the VCXO 7 as stable as the standard signal oscillator. Can be. Therefore, by using the present invention, even an oscillator using a GPS signal timing signal and a crystal oscillator which is inexpensive and requires less maintenance work is equivalent to a standard signal oscillator based on cesium oscillation which requires expensive and regular maintenance work. A highly accurate standard signal oscillator can be provided. In addition, the variation in SA that could not be suppressed by the loop filter can be suppressed, and not only the frequency can be synchronized at high speed, but also the phase can be synchronized at high speed.

[0010]

As described above, according to the first aspect of the present invention, even with an oscillator using a GPS timing signal and a crystal oscillator, which requires less maintenance work and is inexpensive, a high-speed pull-in control unit is provided so that a high-speed frequency can be obtained. Can be synchronized, the time required for synchronization is reduced while removing the influence of SA, and the frequency stability equivalent to that of an expensive cesium oscillator requiring maintenance work can be obtained. According to the second aspect of the present invention, since the amount of change in the VCO control voltage is obtained by averaging the control signal of the D / A converter that generates the signal to be input to the VCO, the amount of change in SA that cannot be suppressed by the loop filter is obtained. Can be suppressed. According to the third aspect of the present invention, the loop filter sets the integral value in the loop filter to 0 when the high-speed pull-in control means obtains the VCO control voltage for generating the target frequency. Not only the synchronization but also the phase can be synchronized at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 shows D when the frequency deviation between input and output is 1 × 10 ^-9.
It is a figure which shows the control value (control bit number) of / A converter, and the value which averaged the control bit number.

FIG. 3 shows a phase variation in an actual input signal to a PLL control unit of an SA and an SA using the PLL control unit of the embodiment;
FIG. 11 is a diagram showing data obtained by recording phase fluctuations in the output signal of the VCXO 7 in which the noise is suppressed for one month.

FIG. 4 is a block diagram showing a configuration of a standard oscillator when a DPPLL is used.

FIG. 5 is a block diagram showing the inside of a PLL control unit 3 in FIG. 4 in further detail;

FIG. 6 is a graph showing a comparison between a frequency response (b) until the frequency converges to a target frequency by a conventional DPPLL and a phase response (a) until the phase difference disappears.

[Explanation of symbols]

1 ... Phase comparator, 3 ... PLL controller, 5 ...
D / A converter, 7 ... voltage controlled crystal oscillator, 9 ...
・ Divider, 11 ・ ・ ・ Switching part, 12 ・ ・ ・ First
, An averaging processing unit, 13 ... an integration operation unit, 14 ... a first adder, 15 ... a multiplier, 16 ... a loop filter, 19 ... a second averaging processing unit, 20: frequency offset control unit, 21: second adder, 22
..High-speed pull-in control unit, A: crystal sensitivity constant (proportional constant), B: integration constant

Claims (3)

[Claims] An output signal of a voltage controlled oscillator (VCO) is compared with a reference input signal from a GPS, and the VCO is controlled using a PLL control unit so that both phases coincide with each other. In the digital processing PLL that removes the influence of the selective availability using the loop filter of the above, the PLL control unit measures the amount of change in the VCO control voltage from the start of the control to the elapse of a predetermined time individually for each VCO in advance. A VCO that generates a target frequency by performing an operation by comparing the obtained control voltage-frequency characteristic data
A digital processing PLL comprising high-speed pull-in control means for obtaining a control voltage. 2. The amount of change in the VCO control voltage is
2. The digital processing PLL according to claim 1, wherein a control signal of a D / A converter that generates a signal to be input to the CO is obtained by averaging. 3. The loop filter according to claim 1, wherein when the high-speed pull-in control unit obtains a VCO control voltage for generating a target frequency, the integrated value in the loop filter is set to zero. Or a digital processing PLL according to 2.