JP6052877B2 - Phase synchronization circuit, time synchronization device, phase synchronization method, and phase synchronization program - Google Patents

Description

  The present invention relates to a phase synchronization circuit, a time synchronization device, a phase synchronization method, and a phase synchronization program, and in particular, a phase capable of realizing stable and highly accurate phase synchronization by shortening the pull-in time even in an asymmetric delay environment. The present invention relates to a synchronization circuit and the like.

  In wireless communication, higher accuracy is required for time synchronization between wireless base stations. In particular, in LTE (Long Term Evolution) and the like, which has begun to spread as the latest high-speed wireless communication standard, time synchronization between wireless base stations is generally required to have an accuracy of 50 ppb or less, but depending on the customer, 1 ppb There is actually a case where high-accuracy synchronization of less than 1/100 million second is required.

  A protocol for realizing such high-precision time synchronization is IEEE 1588v2 established by IEEE (Institute of Electrical and Electronic Engineers) described in Non-Patent Document 1. This protocol was developed on the assumption of a symmetric delay environment in which the uplink and downlink delay configurations are the same, so in an asymmetric delay environment where the uplink and downlink delay configurations are not identical, From the beginning, it has been a problem that accurate time synchronization is difficult.

  In order to satisfy the strict requirement of time synchronization accuracy of “1 ppb” or less in IEEE 1588v2, it is necessary to remove the phase fluctuation corresponding to the phase noise of the packet signal. This phase fluctuation is hereinafter referred to as packet jitter wander (or simply jitter wander). A component having a frequency of 10 Hz or more is packet jitter, and a component having a frequency of less than 10 Hz is packet wander.

  In particular, if there is a packet jitter wander in the 1 pps signal generated on the slave side, the time synchronization accuracy will be greatly deteriorated. The removal of the packet jitter / wander can be broadly divided into two methods: a software removal method at the clock signal generation stage, or a removal method through an external PLL (Phase Locked Loop). There are different ways.

  Of these, the removal method using the former software has been proposed by various vendors, but as required by the ITU-T (International Telecommunication Union-Telecommunication Standardization Sector), only the clock signal generation software requires it. It is generally difficult to satisfy the performance of “1 ppb” or less. For this reason, a clock device such as BC (Boundary Clock) or TC (Transparent Clock) is required between the master device and the slave device.

  On the other hand, since the method of removing by the latter external PLL only needs to suppress the generated packet jitter / wander, there is no need to newly install a device such as BC or TC, and the cost of the entire network is low. Can be suppressed.

  FIG. 8 is an explanatory diagram showing the configuration of the time synchronization apparatus 901 according to the existing technology. The time synchronizer 901 includes an IEEE 1588v2 protocol unit 910, an IEEE 1588v2 packet detection unit 920, and a digital PLL unit 930. The IEEE 1588v2 protocol unit 910 receives a clock signal and a received packet from the outside by communication conforming to the IEEE 1588v2 protocol, and generates a slave time according to this.

  More specifically, the IEEE 1588v2 protocol unit 910 includes a slave time timer function 911 that generates a slave time based on an external clock, a packet capture function 912 that captures a received packet, and a slave time that calculates and outputs a time offset. A time adder 914 that adjusts the slave time by adding a time offset to the slave time generated by the calculation function 913 and the slave time timer function 911 is included.

  The slave time calculation function 913 calculates a time offset based on each numerical value calculated from the received packet and the slave time by the packet capture function 912, and outputs this to the time adder 914. The output from the time adder 914 is output to the digital PLL unit 930 as a time signal (1 pps) before removing the frequency fluctuation component.

  The digital PLL unit 930 has a packet jitter / wander removal performance caused by an asymmetric delay environment and has a holdover function described later, thereby removing a frequency fluctuation component from the time signal (1 pps) output from the time adder 914. Then, a time signal satisfying the required accuracy within 1 ppb is output. In addition, the phase noise cutoff frequency of the digital PLL unit 930 is 1 mHz.

  The digital PLL unit 930 has a general complete digital PLL configuration with a holdover function. That is, a phase comparator 931, a digital amplifier 932, a complete integrator 933, a holdover buffer 934, a selector 935, a D / A converter 936, a VC-OCXO 937, and a frequency divider 938 are included.

  The phase comparator 931 detects the phase difference between the time signal (1 pps) output from the time adder 914 and the reproduction signal divided by the frequency divider 938 from the output signal from the VC-OCXO 937 described later. The digital amplifier 932 amplifies the primary loop signal output from the phase comparator 931. The complete integrator 933 performs amplification and integration processing on the secondary loop signal output from the digital amplifier 932. The holdover buffer 934 realizes a holdover function by averaging the output data from the complete integrator 933.

  In response to an output from a sync message stop monitor function 921 of an IEEE 1588v2 packet detection unit 920, which will be described later, the selector 935 selects an output signal from either the complete integrator 933 or the holdover buffer 934 as a subsequent D / D. Select whether to output to the A converter function 936. The D / A converter 936 converts the digital signal selected by the selector 935 into a voltage signal (analog signal).

  A VC-OCXO 937 (Voltage Controlled / Oven Controlled Crystal Oscillator) converts the voltage signal output from the D / A converter 936 into a frequency signal. The frequency divider 938 divides the output signal from the VC-OCXO 937, and this is finally output to the outside as a time signal that satisfies the required accuracy within 1 ppb, and at the same time, also input to the phase comparator 931. .

  The IEEE 1588v2 packet detection unit 920 includes a sync message stop monitor function 921. The sync message stop monitor function 921 monitors the received packet to detect whether or not the sync message is included in the received packet, and the selector 935 completes the integrator based on the detection result. A control signal for determining which output signal from 933 and the holdover buffer 934 is selected is output.

  More specifically, the selector 935 selects the output signal from the complete integrator 933 in a normal state, but a sync message is detected for a predetermined time given to the received packet in advance. If not, the sync message stop monitor function 921 causes the selector 935 to select the output signal from the holdover buffer 934, and if the sync message is detected again, the output signal from the complete integrator 933 is detected. Select to return to the normal state.

  The phase noise cutoff frequency of the digital PLL unit 930 is 1 mHz (DC loop gain = 2π × 1 mHz = 0.00628: known formula). As a result, the time synchronization apparatus 901 can satisfy the requirement “1 ppb” or less.

  There are following patent documents as technical documents related to this. Among them, Patent Document 1 describes a frequency synthesizer in which two PLL circuits are connected in cascade and the VCO operating current of the first PLL is used as the VCO bias current of the second PLL. Patent Document 2 describes a PLL circuit that configures a PLL loop based on a result of comparing the phase of an input time stamp and a recovered clock.

  Patent Document 3 describes a circuit in which jitter wander is suppressed by configuring three PLLs with a multi-loop synthesizer. Patent Document 4 describes a clock synchronization system in which it is possible to verify on the slave side whether or not time synchronization is accurately achieved. Patent Document 5 describes a timing system in which an error between a clock signal received from a time server on a client side is calculated and converged to zero.

  Patent Document 6 describes a clock synchronization system in which a slave node accumulates packet information from the master side and clock information obtained by reproduction, and performs clock synchronization using these. Patent Document 7 describes a circuit that processes a jitter / wander component and a frequency fluctuation state based on a phase comparison result, and adjusts the loop gain of the PLL means based on this. Non-Patent Document 1 is a standard document of the above-mentioned IEEE 1588v2 protocol.

JP 2000-269810 A JP 2004-248123 A JP 2006-332964 A JP 2011-029918 A Special table 2011-525308 gazette Republished patent WO2009 / 035091 Republished patent WO2010 / 110184

IEEE P1588 TM / D1, “Draft Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems”, June, 2007.

  In order to increase the time accuracy in the time synchronization device 901 based on the IEEE 1588v2 time synchronization system shown in FIG. 8, it has a packet jitter / wander removal performance due to the asymmetric delay environment and the phase noise cutoff frequency is 1 mHz. A digital PLL unit 930 is used.

  However, since the digital PLL section 930 has a PLL input reference of 1 pps, if there is jitter wander in the input signal of 1 pps, it will be “not synchronized” or “synchronized, but stable oscillation from power-on or frequency change” There is a problem that the pull-in time until it becomes becomes very long (specifically, the pull-in time may take more than one day). This is because the shortest PLL control time is 1 second.

  That is, it cannot be determined whether the data subjected to phase comparison in one second is “simple phase shift due to frequency shift” or “packet jitter”, resulting in erroneous synchronization and “not synchronized”. If the filter that removes the packet jitter / wander is provided outside or inside the digital PLL section, this time, “the pull-in time is delayed”. The technology that can solve this problem is not described in any of Patent Documents 1 to 7 and Non-Patent Document 1 described above.

  An object of the present invention is to provide a phase synchronization circuit capable of realizing stable and highly accurate time synchronization by reducing frequency fluctuation to 1 ppb or less and shortening the pull-in time even in a network environment that is an asymmetric delay environment. A synchronization device, a phase synchronization method, and a phase synchronization program are provided.

  In order to achieve the above object, a phase synchronization circuit according to the present invention is a phase synchronization circuit that removes a frequency fluctuation component from an input time signal and outputs it, and determines whether there is packet jitter in the input time signal. And a wander removing means for removing packet wander from the time signal, and the input time signal is determined to have packet jitter. A signal switching unit that passes the time signal through the jitter removal unit and then through the wander removal unit, and directly passes the time signal through the wander removal unit when it is determined that there is no packet jitter in the input time signal. It has the feature.

  In order to achieve the above object, a time synchronization apparatus according to the present invention is a time synchronization apparatus that generates a time signal according to a clock signal and a received packet received from the outside and synchronizes frequency timings between a plurality of bases, A packet receiver that receives a communication packet according to a specific communication protocol and generates a time signal according to the packet, and a packet that constantly monitors the received packet and detects whether a sync message is included in the received packet A phase synchronization circuit according to any one of claims 1 to 7, further comprising: a detection unit; and a phase synchronization circuit that removes a frequency fluctuation component from the time signal according to a sync message. It is a circuit.

  In order to achieve the above object, a phase synchronization method according to the present invention is a phase synchronization circuit that removes a frequency fluctuation component from an input time signal and outputs the phase signal. When the monitoring means determines that the input time signal is determined to have packet jitter, the signal switching means passes the time signal through the jitter removing means to remove the packet jitter, and then passes through the wander removing means to packet. The wander is removed, and when it is determined that there is no packet jitter in the input time signal, the signal switching means passes the time signal directly through the wander removal means to remove the packet wander.

  In order to achieve the above object, a phase synchronization program according to the present invention is a phase synchronization circuit that removes a frequency fluctuation component from an input time signal and outputs the same, and a time input to a processor included in the phase synchronization circuit. Procedures for determining the presence / absence of packet jitter in the signal, procedures for removing packet wander after removing the packet jitter of the time signal when it is determined that the input time signal has packet jitter, input time signal And the step of directly removing the packet wander of the time signal when it is determined that there is no packet jitter.

  As described above, the present invention provides a double PLL circuit called jitter removal means and wander removal means, and when there is packet jitter in the input time signal, the time signal is transferred to the jitter removal means and wander removal means. Since it is configured to pass through both, packet jitter / wander can be effectively removed.

  As a result, even in a network environment that is an asymmetric delay environment, the phase synchronization circuit has an excellent feature that frequency fluctuation can be reduced to 1 ppb or less, and a stable and highly accurate time synchronization can be realized by shortening the pull-in time. , A time synchronization apparatus, a phase synchronization method, and a phase synchronization program can be provided.

It is explanatory drawing shown about the structure of the phase-synchronization circuit which concerns on a basic form. It is explanatory drawing shown about the structure of the time synchronizer which concerns on this embodiment. It is explanatory drawing which shows an example of the radio | wireless communications system using the time synchronizer shown in FIG. FIG. 3 is an explanatory diagram showing the configuration of the digital PLL unit (phase synchronization circuit) shown in FIG. 2 in more detail. It is a graph shown about the change of the output frequency from the VC-TCXO part shown in FIG. It is a graph shown about operation | movement of the slip window monitoring part shown in FIG. 5 is a flowchart showing the operation of the digital PLL unit shown in FIG. It is explanatory drawing shown about the structure of the time synchronizer which concerns on the existing technique.

(Basic form)
Hereinafter, the basic configuration of the present invention will be described with reference to FIG.
First, the basic contents of the basic form will be described, and then more specific contents will be described.
The phase synchronization circuit A according to the basic mode is a phase synchronization circuit that removes and outputs a frequency fluctuation component from the input time signal, and includes phase monitoring means A1 that determines the presence or absence of packet jitter in the input time signal; Jitter removing means A2 for removing packet jitter from the time signal and wander removing means A3 for removing packet wander from the time signal, and when it is determined that the input time signal has packet jitter, The signal switching means A4 that passes the signal through the jitter removal means and then through the wander removal means and directly passes the time signal through the wander removal means when it is determined that there is no packet jitter in the input time signal. is there.
A more detailed configuration of each means will be described as the next embodiment.

(Embodiment)
Then, the structure of embodiment of this invention is demonstrated based on attached FIGS.
First, the basic content of the present embodiment will be described, and then more specific content will be described.
The phase synchronization apparatus (digital PLL unit 30) according to the present embodiment is a phase synchronization circuit that removes a frequency fluctuation component from an input time signal and outputs it, and determines the presence or absence of packet jitter in the input time signal. A phase monitoring unit (1 pps phase monitoring unit 31), a jitter removing unit 33 for removing packet jitter from the time signal, and a wander removing unit 34 for removing the packet wander from the time signal. When it is determined that there is packet jitter, the time signal is passed through the jitter removal means and then passed through the wander removal means. When it is determined that there is no packet jitter in the input time signal, the time signal is directly removed by wander. Signal switching means (1 pps signal switching means 32) to be passed through the means.

  The jitter removing means 33 also includes a multiplying unit 33l for performing a multiplying process for converting the input time signal to a higher frequency, a complete integrator 33d for integrating the multiplied time signal, and the integrated time signal. A D / A converter (D / A converter unit 33g) for converting to an analog signal, a crystal oscillator (VC-TCXO unit 33h) for generating a frequency signal from the analog signal, and a frequency signal generated by dividing the generated frequency signal And a frequency divider that generates a signal having the same frequency as the time signal. This frequency divider divides the generated frequency signal and outputs it to the phase comparison unit, and further divides the output signal of the first stage to obtain the original time signal. And a second stage (1 pps frequency divider 33k) having the same frequency.

  Further, the jitter removing unit 33 compares the phase of the time signal output from the multiplier and the frequency divider to detect the cycle slip, and detects the cycle slip when the cycle slip is detected. A slip window monitoring unit 33b that performs a phase resetting process for forcibly returning the data exceeding the predetermined range to the predetermined range. The slip window monitoring unit 33b performs a phase reset process based on the jitter amplitude information output from the phase monitoring means.

  The jitter removing unit 33 includes a sampling clock multiplying unit 33j that multiplies the time signal output from the crystal oscillator and outputs the signal as an operation clock signal for the phase monitoring unit, the multiplying unit, and the phase comparing unit. Further, the holdover unit 33e that holds the phase information of the complete integrator and the output signal from the complete integrator or the holdover unit are switched based on the external holdover control signal. And a selector 33f.

By providing the above configuration, the phase synchronization apparatus 30 can realize stable highly accurate time synchronization by reducing the frequency fluctuation to 1 ppb or less and shortening the pull-in time.
Hereinafter, this will be described in more detail.

  FIG. 2 is an explanatory diagram showing the configuration of the time synchronization apparatus 1 according to the present embodiment. The time synchronizer 1 includes an IEEE 1588v2 protocol unit 10, an IEEE 1588v2 packet detection unit 20, and a digital PLL unit 30. The IEEE 1588v2 protocol unit 10 and the IEEE 1588v2 packet detection unit 20 are respectively equivalent to the IEEE 1588v2 protocol unit 910 and the IEEE 1588v2 packet detection unit 920 according to the existing time synchronization apparatus 901 shown in FIG. The digital PLL unit 30 will be described later with reference to FIG.

  FIG. 3 is an explanatory diagram showing an example of a wireless communication system 100 using the time synchronization apparatus 1 shown in FIG. The wireless communication system 100 is configured by connecting a master device 110 and a plurality of slave devices 120, 130... Via a packet communication network 140. Each of the master device 110 and the slave devices 120, 130,... Is a ground station of a public wireless communication network, and communicates with a large number of terminal devices (not shown).

  Then, a clock signal and a received packet are transmitted from the master device 110 to each of the slave devices 120, 130... Via the packet communication network 140. Each of the slave devices 120, 130... Is equipped with the time synchronization device 1 shown in FIG. 4, thereby generating and outputting a time signal (slave time) synchronized with the master device 110.

  Although the IEEE 1588v2 protocol includes not only received packets but also transmitted packets, since this embodiment does not particularly depend on transmitted packets, only elements related to received packets are illustrated in FIG. 2, and elements related to transmitted packets are illustrated. Not shown.

  FIG. 4 is an explanatory diagram showing the configuration of the digital PLL unit 30 shown in FIG. 2 in more detail. The digital PLL unit 30 includes a 1 pps phase monitoring unit 31 that detects the presence or absence of packet jitter by monitoring the phase of the 1 pps signal input from the IEEE 1588v2 protocol unit 10, and a jitter removal unit 33 that removes packet jitter from the input 1 pps signal. A 1 pps signal switching unit 32 for switching between a 1 pps signal to which a 1 pps signal is input and a 1 pps signal output from the jitter removing unit 33; and a wander removing unit 34 for removing packet wander.

  The jitter removing means 33 includes a multiplier 33l, a phase comparator 33a, a slip window monitor 33b, a digital amplifier 33c, a complete integrator 33d, a holdover unit 33e, a selector 33f, a D / A converter 33g, and a VC-TCXO. A unit 33h (Voltage Controlled / Temperature Compensated Crystal Oscillator), an 8 kHz frequency divider 33i, a sampling clock multiplier 33j, and a 1 pps frequency divider 33k.

  The multiplier 33l multiplies the 1 pps signal input from the IEEE 1588v2 protocol unit 10 to generate an 8 kHz signal. The phase comparison unit 33a compares the 8 kHz signal output from the multiplication unit 33l with the 8 kHz phase output from the 8 kHz frequency divider 33i, and performs cycle slip (hereinafter simply referred to as slip), which is a phenomenon in which the phase difference vibrates. Detect the presence or absence.

  When the phase comparison unit 33a detects a slip, the slip window monitoring unit 33b performs a process for preventing the maximum / minimum repetition of the output frequency of the VCXO (details will be described later). In this specification, VC-TCXO and VC-OCXO described later are collectively referred to as VCXO.

  The digital amplifier unit 33c amplifies the output signal from the slip window monitoring unit 33b. The complete integrator 33d performs amplification and integration processing of the secondary loop signal output from the digital amplifier unit 33c. The holdover unit 33e holds the phase information and averages the output data from the complete integrator 33d.

  The selection unit 33f selects which output signal from the complete integrator 33d or the holdover unit 33e is to be output to the subsequent D / A converter unit 33g according to the selection signal from the IEEE 1588v2 packet detection unit 20. . The D / A converter unit 33g converts the digital data from the selection unit 33f into an analog signal. The VC-TCXO unit 33h generates a frequency signal from the analog signal output from the D / A converter unit 33g.

  The 8 kHz frequency divider 33i divides the frequency signal output from the VC-TCXO unit 33h to obtain an 8 kHz frequency signal. The sampling clock multiplication unit 33j multiplies the signal from the VC-TCXO unit 33h to generate a sampling clock signal. This sampling clock signal is output to the 1 pps phase monitoring means 31, the multiplication unit 33l, and the phase comparison unit 33a. The 1 pps divider 33k generates a 1 pps signal from the 8 kHz signal output from the 8 kHz divider 33i.

  The wander removing unit 34 includes a phase comparison unit 34a, a slip window monitoring unit 34b, a digital amplifier unit 34c, a complete integrator 34d, a holdover unit 34e, a selection unit 34f, a D / A converter unit 34g, and a VC-OCXO unit 34h (Voltage). Controlled / Oven Controlled Crystal Oscillator, Voltage Control, Oven Controlled Crystal Oscillator), 1 Hz frequency divider 34i, and sampling clock multiplier 34j.

  The phase comparator 34a detects the phase difference between the 1 pps signal output from the 1 pps signal switching means 32 and the 1 Hz signal output from the 1 Hz frequency divider 34i, and detects the presence or absence of slip. When the phase comparison unit 34a detects slip, the slip window monitoring unit 34b performs processing for preventing the maximum / minimum repetition of the output frequency of the VCXO.

  The digital amplifier unit 34c amplifies the output signal from the slip window monitoring unit 34b. The complete integrator 34d performs amplification and integration processing of the secondary loop signal output from the digital amplifier unit 34c. The holdover unit 34e holds the phase information and averages the output data from the complete integrator 34d.

  The selection unit 34f selects which output signal from the complete integrator 34d or the holdover unit 34e is to be output to the subsequent D / A converter unit 33g according to the selection signal from the IEEE 1588v2 packet detection unit 20. . The D / A converter unit 34g converts the digital data from the selection unit 34f into an analog signal. The VC-OCXO unit 34h generates a frequency signal from the analog signal from the D / A converter unit 34g.

  The 1 Hz frequency divider 34i divides the frequency signal output from the VC-OCXO unit 34h into a 1 Hz frequency signal. The frequency signal of 1 Hz becomes the final output signal (time signal) of the digital PLL unit 30 that satisfies the required accuracy within 1 ppb, and is also input to the phase comparison unit 34a as a target for detecting a phase difference. The sampling clock multiplication unit 34j multiplies the signal from the VC-TCXO unit 34h to generate a sampling clock signal, and inputs the sampling clock signal to the phase comparison unit 34a.

(Operation of digital PLL unit)
Next, the operation of the digital PLL unit 30 will be described.
When the 1 pps signal output from the IEEE 1588v2 protocol unit 10 is input to the 1 pps phase monitoring unit 31, the 1 pps phase monitoring unit 31 uses the sampling clock signal from the sampling clock multiplying unit 33 j as a reference for the presence or absence of jitter in the 1 pps signal. And the 1 pps signal switching means 32 is switched according to the detection result. More specifically, it is determined that there is jitter if the fluctuation of a 1 pps signal within an arbitrary μs time is equal to or greater than a threshold value, and that there is no jitter if the fluctuation is equal to or less than the threshold value. Further, the 1 pps phase monitoring means 31 outputs jitter amplitude information described later to the slip window monitoring unit 33b.

  When it is determined that “there is jitter”, the 1 pps phase monitoring unit 31 switches the 1 pps signal switching unit 32 so that the jitter removing unit 33 for removing the jitter is made effective. If it is determined that there is no jitter, the 1 pps phase switching means 31 does not pass the jitter removing means 33 and the 1 pps signal switching means 32 is processed so that the 1 pps signal output from the IEEE 1588v2 protocol unit 10 is directly processed by the wander removing means 34. Switch.

  The operation when the 1 pps phase monitoring unit 31 determines that “jitter is present” will be described. First, the multiplier 33l multiplies the 1 pps signal output from the IEEE 1588v2 protocol unit 10 to obtain an 8 kHz signal. Here, the output frequency is set to 8 kHz (period 125 μs). When a load is applied by the 1 pps frequency divider 33 k, the load (LOAD) is correctly set even if the 1 pps signal has fluctuations such as jitter wander in the order of μs. It is because it can be applied. When it is considered that the fluctuation is small, an output frequency other than 8 kHz may be used.

  The multiplication method of the multiplication unit 33l is based on the sampling clock from the VC-TCXO unit 33h. Therefore, a multiplication error corresponding to 1 bit of the sampling clock is generated, but it can be sufficiently removed by the wander removal means 34 in the subsequent stage, and is not particularly problematic here.

  The phase comparison unit 33a detects the presence or absence of slip by comparing the phase between the 8 kHz signal from the multiplication unit 33l and the 8 kHz signal from the 8 kHz frequency divider 33i, and inputs the result to the slip window monitoring unit 33b. To do.

  FIG. 5 is a graph showing a change in output frequency from the VC-TCXO unit 33h shown in FIG. When the slip is detected by the phase comparison unit 33a, the output frequency from the VC-TCXO unit 33h changes as shown in FIG. 5 and greatly affects the pull-in time. The slip window monitoring unit 33b is provided to avoid this.

  FIG. 6 is a graph showing the operation of the slip window monitoring unit 33b shown in FIG. The horizontal axis represents phase comparison data (unit bits) indicating the phase difference of the 8 kHz signal compared by the phase comparison unit 33a, and the vertical axis represents the output frequency. Here, in the phase comparison data on the horizontal axis, −48 to −32 is defined as “range A”, −32 to +32 is defined as “range B”, and +32 to +48 is defined as “range C”. The slip window monitoring unit 33b operates to forcibly return to the range B when the comparison data output from the phase comparison unit 33a enters the range A or the range C. By this operation, the output frequency of the VC-TCXO unit 33h is prevented from changing as shown in FIG.

  In the example shown in FIG. 6, when the amplitude of the jitter detected by the 1 pps phase monitoring means 31 is not within 16 bits, the output frequency becomes as shown in FIG. 5 unless the phase comparison data is returned to the 32nd bit. Therefore, when the phase comparison data exceeds 48 bits, the slip window monitoring unit 33b outputs a “phase reset” signal that forcibly returns the data to 32 bits to the phase comparison unit 33a.

  At that time, the slip window monitoring unit 33b uses the jitter amplitude information output from the 1 pps phase monitoring means 31, and provides counter information for that amount in advance. In the example shown in FIG. 6, it normally operates with range B, ie, phase comparison data within ± 32 bits, but in practice it expects a 16-bit jitter amplitude (by prior system considerations) A range C is provided. The effect of shortening the pull-in time is obtained by this phase resetting operation.

  Subsequently, the data signal from the slip window monitoring unit 33b is amplified by the digital amplifier unit 33c. This process is generally referred to as a proportional operation process and is known in the art. Thereafter, the data signal output from the digital amplifier unit 33c is input to the complete integrator 33d and integrated. The reason for the complete integrator is to make the stationary phase error zero. This technology is also known.

  Data from the complete integrator 33d is copied to a holdover buffer provided in the holdover unit 33e. Then, the selection unit 33f determines which of the complete integrator 33d and the holdover unit 33e is output to the subsequent stage in accordance with the selection signal from the IEEE 1588v2 packet detection unit 20. In the present embodiment, since the direct attention is not paid to the holdover function, it will not be described in detail.

  The data signal selected by the selector 33f is input to the D / A converter 33g and subjected to digital / analog conversion. The analog data signal output from the D / A converter unit 33g is frequency-converted by the VC-TCXO unit 33h. The frequency signal output from the VC-TCXO unit 33h is input to the 8 kHz frequency divider 33i and the sampling clock multiplication unit 33j.

  The 8 kHz frequency divider 33 i converts the frequency signal from the VC-TCXO unit 33 h into 8 kHz, and the sampling clock multiplication unit 33 j generates a multiplied clock for the operation of the phase comparison unit 33 a and the 1 pps phase monitoring unit 31. The reason for the multiplication is the high-precision control of the PLL and the high accuracy of 1 pps → 8 kHz multiplication. The center frequency of a general VC-TCXO is around 10 MHz. When sampling at 10 MHz, an error of 100 ns occurs. For this reason, the sampling clock multiplying unit 33j reduces the sampling error, for example, by multiplying by 10 to obtain a 10 ns error.

  The 1 pps divider 33k divides the 8 kHz signal from the 8 kHz divider 33i to generate a 1 pps signal. In this case, since it is necessary to synchronize the phase with the original 1 pps signal, a load is applied with the original 1 pps signal, and jitter is removed while ensuring the phase of the 1 pps signal.

  Next, the operation after the 1 pps signal switching means 32 will be described. In the 1 pps signal switching means 32, the 1 pps signal from which jitter has been removed from the 1 pps frequency divider 33k and the original 1 pps signal that has been input are input. Then, which one of the two is output to the wander removing unit 34 is switched by the switching signal output from the 1 pps phase monitoring unit 31. When the 1 pps phase monitoring means 31 determines that “there is jitter above the threshold”, the 1 pps signal from which the jitter has been removed from the 1 pps frequency divider 33k is selected, and it is determined that “there is no jitter above the threshold”. In that case, the original 1 pps signal is selected.

  In the wander removal means 34, the phase comparison unit 34a detects the presence or absence of slip by comparing the phase between the output from the 1pps signal switching means 32 and the 1 Hz signal from the 1 Hz frequency divider 34i, and slips the result. It inputs into the window monitoring part 34b.

  The slip window monitoring unit 34b operates in the same manner as the slip window monitoring unit 33b of the jitter removing unit 33 described above. Also in this case, when the comparison data output from the phase comparison unit 34a falls within the range indicated by C in FIG. By this operation, the output frequency of the VC-OCXO unit 34h is prevented from changing as shown in FIG. However, the slip window monitoring unit 34 b does not particularly perform an operation based on the amplitude information from the 1 pps phase monitoring unit 31. This is because the signal at this stage has already been de-jittered, and it is considered that there is no particular problem with arbitrary slip window monitoring.

  Subsequently, the data signal from the slip window monitoring unit 34b is amplified by the digital amplifier unit 34c. This process is generally referred to as a proportional operation process and is known in the art. Thereafter, the data signal output from the digital amplifier unit 34c is input to the complete integrator 34d and integrated. The reason for the complete integrator is to make the stationary phase error zero. This technology is also known.

  Data from the complete integrator 34d is copied to a holdover buffer provided in the holdover unit 34e. Then, the selection unit 34f determines which one of the complete integrator 34d and the holdover unit 34e is output to the subsequent stage according to the selection signal from the IEEE 1588v2 packet detection unit 20. Again, since the direct attention is not paid to the holdover function, it will not be described in detail.

  The data signal selected by the selection unit 34f is input to the D / A converter unit 34g and subjected to digital / analog conversion. The analog data signal output from the D / A converter unit 34g is frequency-converted by the VC-OCXO unit 34h. The frequency signal output from the VC-OCXO unit 34h is input to the 1 Hz frequency divider 34i and the sampling clock multiplication unit 34j.

  In the 1 Hz frequency divider 34i, the frequency signal from the VC-OCXO unit 34h is converted to 1 Hz, and the final output signal (time signal) of the digital PLL unit 30 satisfying the required accuracy of 1 ppb within the 1 Hz frequency signal At the same time, it is also input to the phase comparator 34a as a target for detecting the phase difference.

  The sampling clock multiplier 34j generates a multiplied clock for the operation of the phase comparator 34a. The reason for multiplication is the high-definition control of the PLL. The center frequency of a general VC-OCXO is around 10 MHz. When sampling is performed at 10 MHz, an error of 100 ns is generated. For example, the sampling error is minimized by multiplying by 10 to obtain an error of 10 ns.

(flowchart)
FIG. 7 is a flowchart showing the operation of the digital PLL unit 30 shown in FIG. When a 1 pps signal is input from the IEEE 1588v2 protocol unit 10 (step S201), the 1 pps phase monitoring means 31 first monitors the 1 pps signal to determine the presence or absence of packet jitter (step S202). The determination result is output to the 1 pps signal switching means 32.

  If it is determined that there is packet jitter, the 1 pps signal switching means 32 switches the input to the jitter removing means 33 side, and the jitter removing means 33 removes the packet jitter of the input 1 pps signal (step S203). The packet wander is removed by means 34 and output (step S204). If it is determined that there is no packet jitter, the 1 pps signal switching unit 32 switches the input to the 1 pps signal side, and the input 1 pps signal is directly removed by the wander removing unit 34 and output (step S204).

  The operations of the 1 pps phase monitoring unit 31 and the 1 pps signal switching unit 32 may be configured in hardware by a logical operation circuit or the like, or may be configured in software by a program or the like operating on a microprocessor.

(Overall operation of the embodiment)
Next, the overall operation of the above embodiment will be described.
The time synchronization method according to this embodiment is a phase synchronization circuit that removes a frequency fluctuation component from an input time signal and outputs it, and the phase monitoring means determines whether or not there is packet jitter in the input time signal ( In FIG. 7, steps S201 to 202), when it is determined that there is packet jitter in the input time signal, the signal switching means passes the time signal through the jitter removing means to remove the packet jitter, and then the wander removing means. The packet wander is removed (steps S203 to S204 in FIG. 7), and when it is determined that there is no packet jitter in the input time signal, the signal switching means passes the time signal directly through the wander removal means and the packet wander. Is removed (FIG. 7, step S204).

Here, each of the above-described operation steps may be programmed to be executable by a computer, and may be executed by a processor provided in the digital PLL unit 30 that directly executes each of the steps. The program may be recorded on a non-temporary recording medium, such as a DVD, a CD, or a flash memory. In this case, the program is read from the recording medium by a computer and executed.
By this operation, this embodiment has the following effects.

  The digital PLL unit 30 according to the present embodiment is provided with a double PLL circuit including a jitter removing unit 33 and a wander removing unit 34. The phase of the time signal (1 pps signal) input by the 1 pps phase monitoring means 31 is monitored to detect the presence or absence of packet jitter. When it is determined that there is packet jitter, the time signal is output by the 1 pps signal switching means 32. Is passed through both the jitter removing means 33 and the wander removing means 34, and when it is determined that there is no packet jitter, the time signal is passed only through the wander removing means 34 by the 1pps signal switching means 32.

  Thereby, in this embodiment, the packet jitter / wander can be effectively removed from the time signal, and the frequency fluctuation can be reduced to 1 ppb or less. In addition, the pull-in time is shortened, and a stable time synchronization operation can be realized. This embodiment does not require the IEEE 1588v2 protocol itself to be changed, and does not require external software for stabilizing the time accuracy, and therefore can be implemented with a very simple configuration.

  More specifically, the jitter removing means 33 multiplies the 1 pps signal input by the multiplier 33l to a frequency of about 8 kHz in order to remove the jitter of the 1 pps signal. By doing so, the control interval of the PLL is accelerated, and jitter removal and high-speed pull-in are possible. However, by multiplying to 8 kHz, the phase of the 1 pps signal becomes free, and the time cannot be synchronized as it is.

  Therefore, in the present embodiment, the 8 kHz signal generated by the frequency division by the 8 kHz frequency divider 33i is further divided by the 1 pps frequency divider 33k, and a load (LOAD) is applied to the original 1 pps signal to obtain the phase of the 1 pps signal. Jitter is removed while ensuring By doing so, even if it is multiplied to 8 kHz, it is possible to completely synchronize the phase with the original 1 pps signal.

  Since this jitter removing means 33 can remove only jitter, a wander removing means 34 is further provided. The wander removing means 34 removes the wander and can reproduce the 1 pps signal from which the fluctuation is removed. Further, the wander removing unit 34 can sufficiently remove a multiplication error corresponding to one bit of the sampling clock that may occur in the jitter removing unit 33.

  The present invention has been described with reference to the specific embodiments shown in the drawings. However, the present invention is not limited to the embodiments shown in the drawings, and any known hitherto provided that the effects of the present invention are achieved. Even if it is a structure, it is employable.

  Regarding the embodiment described above, the main points of the new technical contents are summarized as follows. In addition, although part or all of the said embodiment is summarized as follows as a novel technique, this invention is not necessarily limited to this.

(Supplementary Note 1) A phase synchronization circuit that removes a frequency fluctuation component from an input time signal and outputs it.
Phase monitoring means for determining the presence or absence of packet jitter in the input time signal;
Jitter removing means for removing packet jitter from the time signal;
Wander removal means for removing packet wander from the time signal, and
When it is determined that there is packet jitter in the input time signal, the time signal is passed through the jitter removal means and then through the wander removal means, and it is determined that the input time signal has no packet jitter. A signal switching means for directly passing the time signal through the wander removing means when
A phase synchronization circuit characterized by the above.

(Additional remark 2) The said jitter removal means is
A multiplier for performing a multiplication process for converting the input time signal to a higher frequency;
A complete integrator for integrating the multiplied time signal;
A D / A converter for converting the integrated time signal into an analog signal;
A crystal oscillator that generates a frequency signal from the analog signal;
A frequency divider that divides the generated frequency signal to generate a signal having the same frequency as the original time signal;
The phase synchronization circuit according to appendix 1, wherein:

(Supplementary Note 3) The jitter removing means includes:
A phase comparator for detecting cycle slip by comparing the phase of the time signal output from the multiplier and the frequency divider;
A slip window monitoring unit for performing a phase resetting process for forcibly returning the detected phase comparison data exceeding the predetermined range to the predetermined range when the cycle slip is detected;
The phase synchronization circuit according to appendix 2, characterized by:

(Supplementary Note 4) The frequency divider of the jitter removing unit includes:
A first stage that divides the generated frequency signal and outputs it to the phase comparison unit;
Further comprising a second stage that further divides the output signal of the first stage to have the same frequency as the original time signal;
The phase synchronization circuit according to appendix 2, characterized by:

(Additional remark 5) The said slip window monitoring part of the said jitter removal means performs the said phase reset process based on the jitter amplitude information output from the said phase monitoring means, The additional remark 3 characterized by the above-mentioned. Phase synchronization circuit.

(Additional remark 6) The said jitter removal means is
Having a sampling clock multiplying unit that performs multiplication processing on the time signal output from the crystal oscillator and outputs the clock signal for operation of the phase monitoring unit, the multiplying unit, and the phase comparing unit;
The phase synchronization circuit according to appendix 3, characterized by:

(Supplementary note 7) The jitter removing means comprises:
A holdover section for holding phase information of the complete integrator;
A selection unit that switches whether an output signal from the complete integrator or the holdover unit is passed through the D / A converter based on an external holdover control signal;
The phase synchronization circuit according to appendix 2, characterized by:

(Supplementary Note 8) A time synchronization device that generates a time signal according to a clock signal and a received packet received from the outside, and synchronizes frequency timing between a plurality of bases,
A packet receiver that receives a communication packet according to a specific communication protocol and generates the time signal according to the communication packet;
A packet detector that constantly monitors the received packet and detects whether a sync message is included in the received packet;
A phase synchronization circuit for removing a frequency fluctuation component from the time signal according to the sync message;
With
A time synchronization apparatus, wherein the phase synchronization circuit is the phase synchronization circuit according to any one of appendix 1 to appendix 7.

(Supplementary Note 9) The phase synchronization circuit has a holdover function for holding phase information of the time signal, and
The packet detector controls the operation of the holdover function of the phase synchronization circuit according to the presence or absence of a sync message included in the received packet;
The time synchronizer according to appendix 8, characterized by:

(Supplementary Note 10) In a phase synchronization circuit that removes a frequency fluctuation component from an input time signal and outputs it,
The phase monitoring means determines the presence or absence of packet jitter in the input time signal,
When it is determined that there is packet jitter in the input time signal, the signal switching unit passes the time signal through the jitter removing unit to remove the packet jitter, and then passes through the wander removing unit to remove the packet wander.
If it is determined that there is no packet jitter in the input time signal, the signal switching means passes the time signal directly through the wander removal means to remove the packet wander;
A phase synchronization method characterized by the above.

(Supplementary Note 11) In a phase synchronization circuit that removes a frequency fluctuation component from an input time signal and outputs it,
In the processor included in the phase synchronization circuit,
A procedure for determining the presence or absence of packet jitter in the input time signal;
A procedure for removing packet wander after removing packet jitter of the time signal when it is determined that the input time signal has packet jitter;
And executing a procedure for directly removing the packet wander of the time signal when it is determined that there is no packet jitter in the input time signal,
A phase synchronization program characterized by

  In addition to the LTE ground station described in the embodiment, the present invention can be used particularly in applications that require highly accurate time synchronization, such as a GPS (Global Positioning System) receiver.

A phase synchronization circuit A1 phase monitoring means A2, 33 jitter removal means A3, 34 wander removal means A4 signal switching means 1 time synchronization device 10 IEEE 1588v2 protocol part 20 IEEE 1588v2 packet detection part 30 digital PLL part 33a, 34a phase comparison part 33b, 34b Slip window monitoring unit 33c, 34c Digital amplifier unit 33d, 34d Complete integrator 33e, 34e Holdover unit 33f, 34f Selection unit 33g, 34g D / A converter unit 33h VC-TCXO unit 33i 8kHz frequency divider 33j, 34j Sampling clock Multiplier 33k 1pps frequency divider 33l Multiplier 34h VC-OCXO unit 34i 1Hz frequency divider 100 Wireless communication system 110 Master device 120, 130 Slave device 140 Packet communication network

Claims (10)

A phase synchronization circuit that removes a frequency fluctuation component from an input time signal and outputs it.
Phase monitoring means for determining the presence or absence of packet jitter in the input time signal;
Jitter removing means for removing packet jitter from the time signal;
Wander removal means for removing packet wander from the time signal, and
When it is determined that there is packet jitter in the input time signal, the time signal is passed through the jitter removal means and then through the wander removal means, and it is determined that the input time signal has no packet jitter. A signal switching means for directly passing the time signal through the wander removing means when
A phase synchronization circuit characterized by the above. The jitter removing means
A multiplier for performing a multiplication process for converting the input time signal to a higher frequency;
A complete integrator for integrating the multiplied time signal;
A D / A converter for converting the integrated time signal into an analog signal;
A crystal oscillator that generates a frequency signal from the analog signal;
A frequency divider that divides the generated frequency signal to generate a signal having the same frequency as the original time signal;
The phase-locked loop according to claim 1. The jitter removing means
A phase comparator for detecting cycle slip by comparing the phase of the time signal output from the multiplier and the frequency divider;
A slip window monitoring unit for performing a phase resetting process for forcibly returning the detected phase comparison data exceeding the predetermined range to the predetermined range when the cycle slip is detected;
The phase-locked loop according to claim 2. The frequency divider of the jitter removing means comprises:
A first stage that divides the generated frequency signal and outputs it to the phase comparison unit;
Further comprising a second stage that further divides the output signal of the first stage to have the same frequency as the original time signal;
The phase-locked loop according to claim 3 .   4. The phase synchronization circuit according to claim 3, wherein the slip window monitoring unit of the jitter removing unit performs the phase resetting process based on jitter amplitude information output from the phase monitoring unit. . The jitter removing means
Having a sampling clock multiplying unit that performs multiplication processing on the time signal output from the crystal oscillator and outputs the clock signal for operation of the phase monitoring unit, the multiplying unit, and the phase comparing unit;
The phase-locked loop according to claim 3. The jitter removing means
A holdover section for holding phase information of the complete integrator;
A selection unit that switches whether an output signal from the complete integrator or the holdover unit is passed through the D / A converter based on an external holdover control signal;
The phase-locked loop according to claim 2. A time synchronization device that generates a time signal according to a clock signal and a received packet received from the outside, and synchronizes frequency timing between a plurality of bases,
A packet receiver that receives a communication packet according to a specific communication protocol and generates the time signal according to the communication packet;
A packet detector that constantly monitors the received packet and detects whether a sync message is included in the received packet;
A phase synchronization circuit for removing a frequency fluctuation component from the time signal according to the sync message;
With
8. The time synchronization apparatus according to claim 1, wherein the phase synchronization circuit is the phase synchronization circuit according to claim 1. In the phase synchronization circuit that removes the frequency fluctuation component from the input time signal and outputs it,
The phase monitoring means determines the presence or absence of packet jitter in the input time signal,
When it is determined that there is packet jitter in the input time signal, the signal switching unit passes the time signal through the jitter removing unit to remove the packet jitter, and then passes through the wander removing unit to remove the packet wander.
If it is determined that there is no packet jitter in the input time signal, the signal switching means passes the time signal directly through the wander removal means to remove the packet wander;
A phase synchronization method characterized by the above. In the phase synchronization circuit that removes the frequency fluctuation component from the input time signal and outputs it,
In the processor included in the phase synchronization circuit,
A procedure for determining the presence or absence of packet jitter in the input time signal;
A procedure for removing packet wander after removing packet jitter of the time signal when it is determined that the input time signal has packet jitter;
And executing a procedure for directly removing the packet wander of the time signal when it is determined that there is no packet jitter in the input time signal,
A phase synchronization program characterized by

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