JP2012244290A - Phase comparison circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase comparison circuit that implements phase difference detection at a range of ±180 degrees even if a frequency ratio of input signals is not an integer.SOLUTION: The phase comparison circuit comprises: a phase comparison core circuit 1 for comparing leading edges of an RF signal and a reference signal and generating an up signal or down signal; a mask signal generation circuit 2 for generating a mask control signal MSK1 having a leading edge synchronous with a leading edge of the RF signal preceding a leading edge of the up signal, a pulse width substantially equal to one period of the reference signal, and a period of (M×N+K)/frf, where N, K, M are arbitrary natural numbers expressing a frequency ratio of the RF signal to the reference signal as N+K/M and frf is a frequency of the RF signal; and a signal mask circuit 3 for masking the up signal and down signal generated by the phase comparison core circuit 1 according to the mask control signal MSK1 generated by the mask signal generation circuit 2.

Description

  The present invention relates to a phase comparison circuit applied to a PLL (Phase Locked Loop) circuit.

  In a system having a plurality of PLL circuits to which a common reference signal is input, the accuracy of the phase difference between the output signals of each PLL circuit may be a problem.

  The PLL circuit compares the phase of the input reference signal with the frequency-divided signal of the voltage-controlled oscillator (VCO) output, and feeds back the comparison result to the frequency control terminal of the voltage-controlled oscillator. This is a circuit that obtains a signal obtained by accurately multiplying the reference signal by synchronizing the phase of the output signal (= PLL output signal) with the reference signal.

  Here, when there are variations in the delay time of the buffer amplifier and the frequency divider constituting the PLL circuit and the characteristics of the phase comparison circuit, the phase difference of the PLL output signal with respect to the reference signal varies.

  For example, Patent Document 1 below discloses a method of automatically adjusting a phase difference between output signals for a plurality of PLL circuits having the same reference signal.

  Patent Document 2 below discloses a circuit that compares the phase difference between a reference signal and a PLL output signal as shown in FIG.

  FIG. 6 shows a Hodge Phase Comparison circuit using a flip-flop. This circuit is often used to measure the phase difference between a random data signal and a continuous clock signal. However, if a random data signal is replaced with a clock signal having a different frequency, it can also be used for phase comparison between the reference signal and the PLL output signal.

JP 2004-229020 A JP 2002-252560 A

  In the Hodge phase comparison circuit shown in FIG. 6, the characteristics when a phase comparison is performed using signals having different frequencies as an RF signal and a reference signal will be described below.

  First, FIG. 7 shows a timing chart of the phase comparison circuit when the frequency ratio between the RF signal and the reference signal is an integer (here, the frequency ratio is 2).

  This Hodge phase comparison circuit detects the rising edge of the reference signal and the rising edge of the RF signal immediately after that, and outputs an up signal having a pulse width equal to the time difference between both rising edges. The down signal is always a signal having a pulse width corresponding to a half cycle of the RF signal. As a result, the difference between the pulse width of the up signal and the pulse width of the down signal indicates the time difference (phase difference) between the rising edges of the reference signal and the RF signal.

  FIG. 8 shows an output signal (up signal-down signal integral value) characteristic with respect to the phase difference of the input signal.

  Here, the phase difference of the input signal is expressed with reference to the period of the RF signal. When the phase difference of the input signal exceeds 2π, that is, exceeds the period of the RF signal, the rising edge of the next RF signal is detected, so that the characteristics in the previous 2π range are the same. That is, in this case, the characteristic of the output signal with respect to the phase difference of the input signal has a period of 2π, that is, 360 degrees. In other words, it is possible to detect a phase difference in a range of ± 180 degrees. When the frequency ratio between the RF signal and the reference signal is an integer, the time difference between the rising edge of the reference signal and the rising edge of the next RF signal is always constant. Therefore, the characteristics shown in FIG. 8 are obtained regardless of the value of the frequency ratio. It is done.

  Next, FIG. 9 shows a timing chart of the phase comparison circuit when the frequency ratio between the RF signal and the reference signal is not an integer (here, the frequency ratio is 2.5).

  When the frequency ratio between the RF signal and the reference signal is not an integer, the time difference between the rising edge of the reference signal and the rising edge of the next RF signal is not constant. In the case of the example shown here, two types of time differences are alternately repeated. For this reason, the up signal also outputs pulses of two different widths alternately.

  FIG. 10 shows output signal characteristics with respect to the phase difference of the input signal in this case. Since the average value of the two types of up signals is used for the output signal, the period of the output signal characteristic is halved. That is, it can be seen that the characteristic of the output signal with respect to the phase difference of the input signal has π, that is, a period of 180 degrees, and the detection range of the phase difference is ± 90 degrees.

  Such a condition where the frequency ratio between the RF signal and the reference signal is not an integer is assumed when the RF signal is generated by a fractional PLL using the reference signal as an input, or a frequency-divided signal of the reference signal is used. For example, an RF signal is generated by a PLL.

  Since the conventional phase comparison circuit is configured as described above, there is a problem that the detection range of the phase difference becomes narrower than ± 180 degrees when the frequency ratio between the RF signal and the reference signal is not an integer.

  The present invention has been made to solve the conventional problems, and an object of the present invention is to obtain a phase comparison circuit capable of detecting a phase difference within a range of ± 180 degrees even when the frequency ratio of input signals is not an integer. To do.

  The phase comparison circuit according to the present invention compares the time of rising edge or falling edge of a high frequency signal and a reference signal, and generates an up signal that advances the phase or a down signal that delays the phase according to the comparison result When the frequency ratio between the circuit and the high-frequency signal and the reference signal is N + K / M (where N, K, and M are arbitrary natural numbers) and the frequency of the high-frequency signal is frf, the high-frequency signal immediately before the rise of the up signal Generated by a mask signal generation circuit that generates a mask control signal and a phase comparison core circuit whose pulse width is substantially equal to one cycle of the reference signal and whose cycle is (M × N + K) / frf A signal mask circuit for masking the up signal and the down signal generated according to the mask control signal generated by the mask signal generation circuit; It includes those were.

  According to the present invention, the up signal and the down signal generated by the phase comparison core circuit are masked according to the mask control signal by the signal mask circuit, so that the frequency ratio between the high frequency signal and the reference signal is an integer or not an integer. First, the pulse width of the up signal output from the signal mask circuit does not change every time and becomes a constant value. In other words, only the comparison result of the part where the rising timing relationship between the reference signal and the high frequency signal is equal is output. Therefore, in this case, the characteristic of the output signal with respect to the phase difference of the input signal has a period of 2π, that is, 360 degrees, and the phase difference is detected within a range of ± 180 degrees even when the frequency ratio of the input signal is not an integer. There is an effect that a phase comparison circuit capable of achieving the above can be obtained.

It is a circuit diagram which shows the phase comparison circuit by Embodiment 1 of this invention. 6 is a timing chart showing an operation when the frequency ratio between the RF signal and the reference signal is not an integer in the phase comparison circuit according to the first embodiment of the present invention. It is a characteristic view which shows the output signal characteristic with respect to the phase difference of an input signal in case the frequency ratio of RF signal and a reference signal is not an integer in the phase comparison circuit by Embodiment 1 of this invention. It is a circuit diagram which shows the phase comparison circuit by Embodiment 2 of this invention. It is a timing chart which shows operation | movement when the frequency ratio of RF signal and a reference signal is not an integer in the phase comparison circuit by Embodiment 2 of this invention. It is a circuit diagram which shows the conventional phase comparison circuit. It is a timing chart which shows operation | movement in case the frequency ratio of RF signal and a reference signal is an integer in the conventional phase comparison circuit. It is a characteristic view which shows the output signal characteristic with respect to the phase difference of an input signal in case the frequency ratio of RF signal and a reference signal is an integer in the conventional phase comparison circuit. It is a timing chart which shows operation | movement when the frequency ratio of RF signal and a reference signal is not an integer with the conventional phase comparison circuit. It is a characteristic diagram which shows the output signal characteristic with respect to the phase difference of an input signal in case the frequency ratio of RF signal and a reference signal is not an integer in the conventional phase comparison circuit.

Embodiment 1 FIG.
1 is a circuit diagram showing a phase comparison circuit according to a first embodiment of the present invention.
In FIG. 1, this phase comparison circuit is roughly classified into a phase comparison core circuit 1, a mask signal generation circuit 2, and a signal mask circuit 3.

  The phase comparison core circuit 1 has the same configuration as the Hodge phase comparison circuit shown in FIG. That is, the D flip-flop circuit (referred to as DFF) 6 latches the reference signal input from the terminal 4 at the rising edge of the RF signal input from the terminal 5, and the DFF 7 is the RF signal input from the terminal 5. The output signal of DFF6 is latched at the falling edge of.

The AND circuit 8 calculates the logical product of the reference signal input from the terminal 4 and the inverted output signal of the DFF 6, and the output signal becomes the up signal UP 1 that is the output of the phase comparison core circuit 1.
The AND circuit 9 calculates the logical product of the output signal of the DFF 6 and the inverted output signal of the DFF 7, and the output signal becomes the down signal DN 1 that is another output of the phase comparison core circuit 1.

  The mask signal generation circuit 2 generates a mask control signal MSK1, and includes an OR circuit 13, an AND circuit 14, and a counter circuit 15.

  The OR circuit 13 calculates the logical sum of the mask control reset signal input from the terminal 12 and the mask control signal MSK1 output from the counter circuit 15. The AND circuit 14 calculates a logical product of the down signal DN1 output from the phase comparison core circuit 1 and the output signal from the OR circuit 13, and the output signal becomes a counter reset signal RS1 for resetting the counter circuit 15.

  After the counter circuit 15 is reset by the counter reset signal RS1, it counts the rising edge of the input clock, that is, the RF signal, and when it reaches the count set value (CNT) set from the terminal 10, the mask control signal MSK1. Is output.

  Here, the mask control signal MSK1 is a signal synchronized with the RF signal, and the rising edge of this signal coincides with the rising edge of the RF signal immediately before the rising edge of the up signal. The pulse width of the mask control signal MSK1 is substantially equal to one cycle of the reference signal, and the cycle is the frequency ratio between the RF signal and the reference signal, N + K / M (where N, K, and M are arbitrary natural numbers) ), It is (M × N + K) / frf (where frf is the frequency of the RF signal).

  When the pulse width setting value (PW) is set from the terminal 11, the pulse width of the mask control signal MSK1 becomes PW / frf using the pulse width setting value (PW). Here, if the count setting value (CNT) is (M × N + K−1) and the pulse width setting value (PW) is N, the defined mask control signal MSK1 is obtained.

  The signal mask circuit 3 masks the up signal UP1 and the down signal DN1 output from the phase comparison core circuit 1 with the mask control signal MSK1 output from the mask signal generation circuit 2.

The AND circuit 16 outputs the logical product of the up signal UP1 output from the phase comparison core circuit 1 and the mask control signal MSK1 output from the mask signal generation circuit 2 from the terminal 18 as an up signal.
The AND circuit 17 outputs a logical product of the down signal DN1 output from the phase comparison core circuit 1 and the mask control signal MSK1 output from the mask signal generation circuit 2 from the terminal 19 as a down signal.

Next, the operation will be described.
FIG. 2 is a timing chart when the frequency ratio between the RF signal and the reference signal is not an integer (here, the frequency ratio is 2.5). Since N = 2, M = 2, and K = 1, the count setting value (CNT) set in the mask signal generation circuit 2 is 4, and the pulse width setting value (PW) is 2.

First, when the mask control reset signal is “H”, the down signal DN1 is output as it is as the counter reset signal RS1.
Since this down signal DN1 is a down signal of the Hodge phase comparison circuit shown in FIG. 6, a pulse is output at every cycle of the reference signal. For this reason, since the counter circuit 15 is reset every two or three periods of the RF signal, the count value does not reach 4 and the mask control signal MSK1 is not output.

  Next, when the mask control reset signal is set to “L” and the reset of the mask signal generation circuit 2 is released, the output of the OR circuit 13 becomes “L”, so the counter reset signal RS1 remains “L”. . That is, since the counter circuit 15 is not reset, the counter circuit 15 counts up, and when the count value becomes 4, the mask control signal MSK1 becomes “H”.

  Since the pulse width of the mask control signal MSK1 is PW = 2, it is a length corresponding to two periods of the RF signal. Here, while the mask control signal MSK1 is “H”, the down signal DN1 is output, and this pulse passes through the AND circuit 14 to reset the counter circuit 15. Thereafter, the above operation is repeated.

  Therefore, the mask signal generation circuit 2 rises in synchronization with the RF signal and coincides with the rise of the RF signal immediately before the rise of the up signal UP1, the pulse width is substantially equal to one cycle of the reference signal, and the cycle is It can be seen that a mask control signal MSK1 of (M × N + K) / frf can be generated.

  By using the mask control signal MSK1, the up signal UP1 and the down signal DN1 output from the phase comparison core circuit 1 are masked, so that the pulse width of the output up signal does not change every time and becomes a constant value. This principle is as follows.

  When the frequency ratio between the RF signal and the reference signal is N + K / M, the time of (M × N + K) cycles of the RF signal is equal to the time of M cycles of the reference signal. That is, the relationship of (M × N + K) / frf = M / fref is established. In addition, the pulse width of the up signal output from the phase comparison core circuit 1 fluctuates at a cycle of (M × N + K) / frf (= M / fref). Therefore, by selecting the up signal only once in the time of (M × N + K) / frf, the width of the selected pulse becomes constant.

FIG. 3 shows the output signal characteristics with respect to the phase difference of the input signal of the phase comparator in this case.
According to FIG. 3, it has a period of 2π, that is, 360 degrees, and it can be seen that a phase difference in a range of ± 180 degrees can be detected.

  In the first embodiment, the Hodge phase comparison circuit is used as the phase comparison core circuit 1. However, the rising or falling edge times of the input RF signal and the reference signal are compared, and the comparison result is determined. As long as the circuit generates an up signal for advancing the phase or a down signal for delaying the phase, another circuit may be used.

  The mask signal generation circuit 2 also rises in synchronization with the RF signal, coincident with the rise of the RF signal immediately before the rise of the up signal UP1, and the pulse width is substantially equal to one cycle of the reference signal. Any other circuit may be used as long as it can generate the mask control signal MSK1 to be (M × N + K) / frf.

  As described above, according to the first embodiment, the up signal UP1 and the down signal DN1 generated by the phase comparison core circuit 1 are masked according to the mask control signal MSK1 by the signal mask circuit 3, thereby Regardless of whether the frequency ratio to the reference signal is an integer or not, the pulse width of the up signal output from the signal mask circuit 3 does not change every time and becomes a constant value. In other words, only the comparison result of the part where the rising timing relationship between the reference signal and the RF signal is equal is output. Therefore, in this case, the characteristic of the output signal with respect to the phase difference of the input signal has a period of 2π, that is, 360 degrees, and the phase difference is detected within a range of ± 180 degrees even when the frequency ratio of the input signal is not an integer. There is an effect that a phase comparison circuit capable of achieving the above can be obtained.

Embodiment 2. FIG.
In the first embodiment, the up signal UP1 and the down signal DN1 generated by the phase comparison core circuit 1 are masked by the signal mask circuit 3 in accordance with the mask control signal MSK1, but in the second embodiment, the phase comparison core circuit By masking the reference signal which is input 1 according to the mask control signal by the signal mask circuit, the phase difference can be detected within a range of ± 180 degrees even when the frequency ratio of the input signal is not an integer. is there.

4 is a circuit diagram showing a phase comparison circuit according to Embodiment 2 of the present invention.
In FIG. 4, this phase comparison circuit is roughly classified into a mask signal generation circuit 21, a signal mask circuit 22, and a phase comparison core circuit 1.

  The mask signal generation circuit 21 generates a mask control signal MSK 2 and includes an OR circuit 23 and a counter circuit 24.

  The OR circuit 23 calculates a logical sum of the mask control reset signal input from the terminal 12 and the mask control signal MSK2 output from the counter circuit 24, and the output signal resets the counter reset signal RS2 that resets the counter circuit 24. Become.

  After the counter circuit 24 is reset by the counter reset signal RS2, the counter circuit 24 counts the falling edge of the input clock, that is, the reference signal. When the counter circuit 24 reaches the count setting value (CNT) set from the terminal 10, the mask control signal Outputs MSK2.

  Here, the mask control signal MSK2 is a signal synchronized with the reference signal, and rises in accordance with the fall of the reference signal. The pulse width of the mask control signal MSK2 is substantially equal to one period of the reference signal, and the period is M / fref. However, the frequency ratio between the RF signal and the reference signal is N + K / M, and fref is the frequency of the reference signal.

  Here, if the count set value (CNT) is set to (M-1), the defined mask control signal MSK2 is obtained.

The signal mask circuit 22 masks the reference signal input from the terminal 4 with the mask control signal MSK2 generated by the mask signal generation circuit 21.
In the signal mask circuit 22, the AND circuit 25 outputs a logical product of the reference signal and the mask control signal MSK2 as the signal mask circuit output signal REF2.

  The phase comparison core circuit 1 has the same configuration as the Hodge phase comparison circuit shown in FIG. However, the DFF 6 latches the signal mask circuit output signal REF 2 input from the signal mask circuit 22 at the rising edge of the RF signal input from the terminal 5.

Next, the operation will be described.
FIG. 5 is a timing chart when the frequency ratio between the RF signal and the reference signal is not an integer (here, the frequency ratio is 2.5). Since N = 2, M = 2, and K = 1, the count setting value (CNT) set in the mask signal generation circuit 21 is 1.

First, when the mask control reset signal is “H”, the counter circuit 24 is always reset, so the mask control signal MSK2 remains “L”.
That is, since the reference signal is masked by the signal mask circuit 22, no reference signal is input to the phase comparison core circuit 1, and neither an up signal nor a down signal is output.

  Next, when the mask control reset signal is set to “L” and the reset of the mask signal generation circuit 21 is released, the counter reset signal RS1 that is the output of the OR circuit 23 becomes “L”. That is, although the counter circuit 24 starts counting, since the count setting value (CNT) is 1, the mask control signal MSK2 becomes “H” at the fall of the next reference signal. At the same time, the counter circuit 24 is reset by “H” of the mask control signal MSK2.

  Thereafter, after the mask control signal MSK2 continues to be “H” for a time corresponding to one cycle of the reference signal, the mask control signal MSK2 becomes “L”, the reset of the counter circuit 24 is released, and counting is started again. Thereafter, the above operation is repeated.

  Therefore, in the mask signal generation circuit 21, in synchronization with the reference signal, the mask control signal rises in synchronization with the fall of the reference signal, the pulse width is equal to one period of the reference signal, and the period is M / fref. It can be seen that MSK2 can be generated.

  By using the mask control signal MSK2 to mask the reference signal that is input to the phase comparison core circuit 1, the pulse width of the up signal output from the phase comparison core circuit 1 does not change every time and becomes a constant value. This principle is the same as in the first embodiment.

In this case, the output signal characteristic with respect to the phase difference of the input signal of the phase comparator is the same as in FIG.
According to FIG. 3, it has a period of 2π, that is, 360 degrees, and it can be seen that a phase difference in a range of ± 180 degrees can be detected.

  In the second embodiment, the Hodge phase comparison circuit is used as the phase comparison core circuit 1. However, the rising or falling edge times of the input RF signal and the reference signal are compared, and the comparison result is determined. As long as the circuit generates an up signal for advancing the phase or a down signal for delaying the phase, another circuit may be used.

  The mask signal generation circuit 21 also rises in synchronization with the fall of the reference signal in synchronization with the reference signal, the mask width is equal to one cycle of the reference signal, and the cycle is M / fref. Other circuits may be used as long as they can generate MSK2.

  As described above, according to the second embodiment, the reference signal that is the input of the phase comparison core circuit 1 is masked by the signal mask circuit 22 in accordance with the mask control signal MSK2, so that the frequency of the RF signal and the reference signal is increased. Regardless of whether the ratio is an integer or non-integer, the pulse width of the up signal output from the phase comparison core circuit 1 does not change every time and becomes a constant value. In other words, only the comparison result of the part where the rising timing relationship between the reference signal and the RF signal is equal is output. Therefore, in this case, the characteristic of the output signal with respect to the phase difference of the input signal has a period of 2π, that is, 360 degrees, and the phase difference is detected within a range of ± 180 degrees even when the frequency ratio of the input signal is not an integer. There is an effect that a phase comparison circuit capable of achieving the above can be obtained.

  In the present invention, within the scope of the invention, any combination of each embodiment, any modification of any component of each embodiment, or omission of any component in each embodiment is possible. .

  DESCRIPTION OF SYMBOLS 1 Phase comparison core circuit, 2,21 Mask signal generation circuit, 3,22 Signal mask circuit, 4,5,10-12,18,19 terminal, 6,7 D flip-flop circuit, 8, 9, 14, 16, 17, 25 AND circuit, 13, 23 OR circuit, 15, 24 counter circuit.

Claims (8)

A phase comparison core circuit that compares the time of the rising edge or the falling edge of the high-frequency signal and the reference signal and generates an up signal that advances the phase or a down signal that delays the phase according to the comparison result;
When the frequency ratio between the high frequency signal and the reference signal is N + K / M (where N, K, and M are arbitrary natural numbers) and the frequency of the high frequency signal is frf, the high frequency signal rises immediately before the rise of the up signal. A mask signal generation circuit that generates a mask control signal that rises synchronously and has a pulse width substantially equal to one cycle of the reference signal and a cycle of (M × N + K) / frf;
A phase comparison circuit comprising: a signal mask circuit that masks an up signal and a down signal generated by the phase comparison core circuit according to a mask control signal generated by the mask signal generation circuit. The phase comparison core circuit includes:
A first D flip-flop circuit that latches the reference signal at the rising edge of the high-frequency signal;
A second D flip-flop circuit that latches the output signal of the first D flip-flop circuit at a falling edge of a high-frequency signal;
A first AND circuit that calculates a logical product of a reference signal and an inverted output signal of the first D flip-flop circuit, and generates an up signal;
And a second AND circuit that calculates a logical product of an output signal of the first D flip-flop circuit and an inverted output signal of the second D flip-flop circuit and generates a down signal. The phase comparison circuit according to claim 1. The mask signal generation circuit includes:
An OR circuit that calculates a logical sum of a mask control reset signal input from the outside and a mask control signal generated by the mask signal generation circuit;
A third AND circuit that calculates a logical product of a down signal generated by the phase comparison core circuit and a logical sum signal calculated by the OR circuit;
The high frequency signal operates as a clock, is reset by a logical product calculated by the third AND circuit, counts the rising edge of the clock, and when the count value reaches M × N + K−1, the pulse width becomes N / N 2. The phase comparison circuit according to claim 1, further comprising a counter circuit that outputs a frf mask control signal. The signal mask circuit is
A fourth AND circuit that calculates a logical product of the up signal generated by the phase comparison core circuit and the mask control signal generated by the mask signal generation circuit;
2. The fifth AND circuit according to claim 1, further comprising a fifth AND circuit that calculates a logical product of the down signal generated by the phase comparison core circuit and the mask control signal generated by the mask signal generation circuit. Phase comparison circuit. When the frequency ratio between the high-frequency signal and the reference signal is N + K / M (where N, K, and M are arbitrary natural numbers) and the frequency of the reference signal is fref, the pulse rises in synchronization with the fall of the reference signal. A mask signal generating circuit for generating a mask control signal having a width equal to one cycle of the reference signal and a cycle of M / fref;
A signal mask circuit for masking a reference signal according to a mask control signal generated by the mask signal generation circuit;
A phase comparison core circuit that compares the time of a rising edge or a falling edge of a reference signal output from the signal mask circuit with a high-frequency signal and generates an up signal that advances the phase or a down signal that delays the phase according to the comparison result And a phase comparison circuit. The mask signal generation circuit includes:
An OR circuit that calculates a logical sum of a mask control reset signal input from the outside and a mask control signal generated by the mask signal generation circuit;
Operates using the reference signal as a clock, is reset by a signal based on the logical sum calculated by the OR circuit, counts the falling edge of the clock, and when the count value reaches M-1, the mask control with a pulse width of 1 / fref 6. The phase comparison circuit according to claim 5, further comprising a counter circuit that outputs a signal. The signal mask circuit is
6. The phase comparison circuit according to claim 5, further comprising a first AND circuit that calculates a logical product of a reference signal and a mask control signal generated by the mask signal generation circuit. The phase comparison core circuit includes:
A first D flip-flop circuit that latches a reference signal output from the signal mask circuit at a rising edge of a high-frequency signal;
A second D flip-flop circuit that latches the output signal of the first D flip-flop circuit at a falling edge of a high-frequency signal;
A second AND circuit that calculates a logical product of a reference signal output from the signal mask circuit and an inverted output signal of the first D flip-flop circuit, and generates an up signal;
And a third AND circuit that calculates a logical product of an output signal of the first D flip-flop circuit and an inverted output signal of the second D flip-flop circuit and generates a down signal. The phase comparison circuit according to claim 5.

Images