JP5883984B1 - Oscillation circuit, PLL circuit, and signal processing device - Google Patents

Abstract

[PROBLEMS] To achieve both high speed and stability. A pulse width of a reference signal (P1) input to a phase comparator (11) of a PLL circuit and a comparison signal (P3) output from an oscillator (13) of the PLL circuit and input to a phase comparator. A pulse width comparator (15) for detecting a difference between the pulse width and the signal from the phase comparator and the switch from which the signal from the pulse width comparator is input to the oscillator (16) The oscillator to which the signal from the pulse width comparator is input outputs an oscillation frequency signal (P2) determined based on the difference between the pulse widths detected by the pulse width comparator, and the pulse width comparison When the signal from the device is input to the oscillator, the reference signal and the comparison signal are in phase. [Selection] Figure 1

Description

  The present invention relates to an oscillation circuit, a PLL circuit, and a signal processing device.

  A PLL (Phase Locked Loop) circuit is an electronic circuit that outputs a signal synchronized with the phase of an input reference signal. The PLL circuit includes a phase comparator, a loop filter, an oscillator, and a frequency divider. The phase comparator detects a phase difference between the reference signal and the signal from the frequency divider, and outputs an error signal proportional to the detected phase difference. The loop filter averages the error signal output from the phase comparator and outputs a DC signal with a small AC component. The loop filter is, for example, a low pass filter. The oscillator outputs a signal having a frequency corresponding to the DC signal (DC voltage) output from the loop filter. The frequency divider divides the signal output from the oscillator. The frequency-divided signal is input (feedback) to the phase comparator.

  In this way, the oscillator has a signal of the oscillation frequency determined by the loop filter based on the phase difference between the reference signal input to the phase comparator and the signal output from the oscillator and divided by the frequency divider. Is output. As a result, the PLL circuit is in a state in which a signal synchronized with the phase of the reference signal input to the phase comparator is output from the oscillator. This state is a locked state of the PLL circuit. On the other hand, the unlocked state of the PLL circuit is a state in which a signal that is not synchronized with the phase of the reference signal input to the phase comparator is output from the oscillator.

  The PLL circuit operates to maintain the locked state. That is, when the PLL circuit shifts from the locked state to the unlocked state, the PLL circuit operates to shift to the locked state. That is, for example, the PLL circuit enters an unlocked state when the phase of the reference signal is shifted from that of the signal output from the oscillator due to a change in the input reference signal. In the unlocked PLL circuit, the signal of the oscillation frequency determined by the loop filter so as to eliminate the phase difference between the reference signal and the signal output from the oscillator is output from the oscillator and shifts to the locked state.

  In the PLL circuit, the stabilization time and output jitter are in a trade-off relationship. The stabilization time is the time from when the reference signal is input until the signal having the same phase as the reference signal is output from the oscillator. Output jitter is a shift in the period between the reference signal and the signal output from the oscillator. The stabilization time and output jitter depend on the cutoff frequency of the loop filter. That is, if the cut-off frequency of the loop filter is set high so that the stabilization time is shortened, the output jitter increases. In other words, the frequency of the signal output from the oscillator once matches the frequency of the reference signal, and the reference signal and the signal output from the oscillator have the same phase, but then these signals are out of phase and stable. do not do. On the other hand, if the cut-off frequency of the loop filter is set low so that the output jitter is small, the stabilization time becomes long. That is, the frequency of the signal output from the oscillator changes slowly and matches the frequency of the reference signal, and then stabilizes. Under such circumstances, both high speed and stability of the PLL circuit are required.

  There have been proposed PLL circuits including a plurality of loop filters that select a loop filter according to a phase difference between a reference signal and a signal output from an oscillator (for example, Patent Documents). 1).

JP-A-9-284132

  However, if a plurality of loop filters are provided corresponding to the phase difference between the reference signal and the signal output from the oscillator in order to achieve both high speed and stability, the configuration of the PLL circuit becomes complicated. In addition, when the plurality of loop filters are switched in stages according to the phase difference between the reference signal and the signal output from the oscillator, the stabilization time becomes longer.

  The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a PLL circuit capable of realizing both high speed and stability.

The oscillation circuit according to the present invention calculates the difference between the pulse width of the reference signal input to the phase comparator of the PLL circuit and the pulse width of the comparison signal output from the oscillator of the PLL circuit and input to the phase comparator. A pulse width comparator to detect, a signal from the phase comparator, and a switch that inputs one of the signals from the pulse width comparator to the oscillator, and the comparison signal is counted by the comparison counter Generated by the pulse width comparator is an oscillation frequency signal determined based on the difference between the pulse widths detected by the pulse width comparator and has the same pulse width as the reference signal. A width signal is output, and when the signal from the pulse width comparator is input to the oscillator, the count value of the comparison counter is reset so that the reference signal and the comparison signal have the same phase.

  According to the present invention, both high speed and stability can be realized.

It is a block diagram of the oscillation circuit and PLL circuit concerning this invention. It is a flowchart of the signal processing of the PLL circuit of FIG. 2 is a flowchart of a pulse width comparison process of the PLL circuit of FIG. 2 is a flowchart of phase comparison processing of the PLL circuit of FIG. 2 is a timing chart showing the relationship between a reference signal and a comparison signal input to the PLL circuit of FIG. 6 is a timing chart showing another relationship between a reference signal and a comparison signal input to the PLL circuit of FIG. 1.

  Hereinafter, embodiments of an oscillation circuit, a PLL circuit, and a signal processing device according to the present invention will be described with reference to the drawings.

● Configuration of oscillation circuit and PLL circuit ●
FIG. 1 is a block diagram of an oscillation circuit and a PLL circuit according to the present invention.
The PLL circuit C1 according to the present invention includes a phase comparator 11, a loop filter 12, an oscillator 13, a frequency divider 14, and an oscillation circuit C2 according to the present invention. The oscillation circuit C2 includes a pulse width comparator 15 and a switch 16. The oscillation circuit C2 constitutes a part of the PLL circuit C1.

  The phase comparator 11, the loop filter 12, the oscillator 13, and the frequency divider 14 are the same as those provided in the conventional PLL circuit. That is, the PLL circuit C1 is different from the conventional PLL circuit in that it includes the oscillation circuit C2.

  The phase comparator 11 detects a phase difference between the reference signal P1 input from an external device (not shown) and the comparison signal P3 output from the frequency divider 14, and an error proportional to the detected phase difference. Output a signal.

  For example, the reference signal P1 is generated by counting a 27 MHz reference clock once.

  The comparison signal P3 is generated, for example, by counting a 54 MHz comparison clock once every two times.

  The loop filter 12 averages the error signal output from the phase comparator 11 and outputs a DC second control signal P4 having a small AC component. The second control signal P4 will be described later.

  The oscillator 13 outputs an oscillation signal P2 having a frequency corresponding to the control signal P6 output from the switch 16. The control signal P6 will be described later.

  The frequency divider 14 divides the oscillation signal P7 output from the oscillator 13 and outputs a comparison signal P3. The comparison signal P3 is input to the phase comparator 11 and the pulse width comparator 15.

  The pulse width comparator 15 detects a pulse width difference between the pulse width of the reference signal P1 and the pulse width of the comparison signal P3, and outputs a first control signal P5 proportional to the detected pulse width difference. To do. The first control signal P5 will be described later.

  The pulse width comparator 15 includes a first counter, a second counter, and a subtracter.

  The first counter measures the pulse width of the reference signal P1 by detecting and counting the falling edge of the reference signal P1.

  The second counter measures the pulse width of the oscillation signal P2 by detecting and counting the falling edge of the comparison signal P3.

  The subtractor calculates the difference between the pulse width of the reference signal P1 and the pulse width of the comparison signal P3 based on the difference between the count value of the first counter and the count value of the second counter. That is, for example, the subtracter subtracts the count value of the first counter from the counter value of the second counter, or subtracts the count value of the second counter from the count value of the first counter. And the difference between the pulse width of the comparison signal P3.

  The count value of the first counter and the count value of the second counter are counted using, for example, a measurement clock of 27 MHz.

  The switch 16 inputs either the second control signal P4 from the loop filter 12 or the first control signal P5 from the pulse width comparator 15 to the oscillator 13. The switch 16 determines the signal input to the oscillator 13 as one of the second control signal P4 and the first control signal P5 based on the phase difference between the reference signal P1 and the comparison signal P3. That is, for example, the switch 16 inputs the second control signal P4 to the oscillator 13 when the phase difference between the reference signal P1 and the comparison signal P3 is equal to or smaller than the reference value, and performs the first control when the phase difference is larger than the reference value. The signal P5 is input to the oscillator 13. That is, when the phase difference between the reference signal P1 and the comparison signal P3 is equal to or less than the reference value, the control signal P6 is the second control signal P4. On the other hand, when the phase difference between the reference signal P1 and the comparison signal P3 is larger than the reference value, the control signal P6 is the first control signal P5. The reference value used by the switch 16 for selecting the second control signal P4 and the first control signal P5 is set in the switch 16 in advance.

  The oscillator 13 to which the second control signal P4 is input outputs an oscillation signal P2 having an oscillation frequency determined by the loop filter 12 according to the phase difference between the reference signal P1 and the comparison signal P3. The oscillation frequency determined by the loop filter 12 is a value that decreases the phase difference between the reference signal P1 and the comparison signal P3.

  The oscillator 13 to which the first control signal P5 is input outputs an oscillation signal P2 having an oscillation frequency determined by the pulse width comparator 15 according to the difference between the pulse width of the reference signal P1 and the pulse width of the comparison signal P3. . The oscillation frequency determined by the pulse width comparator 15 is a value that decreases the difference between the pulse width of the reference signal P1 and the pulse width of the comparison signal P3.

  That is, the pulse width comparator 15 holds the correspondence between the pulse width difference and the oscillation frequency. Based on this correspondence, the detected pulse width of the reference signal P1 and the pulse width of the comparison signal P3 The oscillation frequency (first setting value described later) corresponding to the difference is determined.

● Oscillator and PLL circuit operation ●
FIG. 2 is a flowchart of signal processing of the PLL circuit C1.
The PLL circuit C1 performs a pulse width comparison process (S1) and a phase comparison process (S2) while the reference signal P1 and the comparison signal P3 are input.

FIG. 3 is a flowchart of the pulse width comparison process (S1).
When the pulse width comparator 15 acquires the reference signal P1 (S11), the pulse width of the reference signal P1 is counted (measured) using the first counter (S13). Similarly, when the pulse width comparator 15 acquires the comparison signal P3 (S12), the pulse width of the comparison signal P3 is counted using the second counter (S14).

  Next, the pulse width comparator 15 detects the difference between the pulse width of the reference signal P1 and the pulse width of the comparison signal P3 (S15). The difference in pulse width is detected (calculated) by the subtractor of the pulse width comparator 15 using the count value of the first counter and the count value of the second counter. That is, the subtracter subtracts the count value of the first counter from the count value of the second counter, or subtracts the count value of the second counter from the count value of the first counter, so that the pulse width of the reference signal P1 And the difference between the pulse width of the comparison signal P3.

  Next, the pulse width comparator 15 calculates the first set value based on the difference between the pulse width of the reference signal P1 calculated by the subtracter and the pulse width of the comparison signal P3 (S16). The first set value is a value that determines the oscillation frequency of the oscillator 13. That is, the oscillator 13 in which the first set value is set outputs an oscillation signal P2 having an oscillation frequency corresponding to the first set value. The pulse width comparator 15 outputs a first control signal P5 corresponding to the first set value to the switch 16. That is, when the oscillator 13 acquires the first control signal P5 from the switch 16, the oscillator 13 outputs the oscillation signal P2 having an oscillation frequency corresponding to the first set value.

FIG. 4 is a flowchart of the phase comparison process (S2).
The phase comparator 11 acquires the reference signal P1 and the comparison signal P3 (S21, S22), and detects the phase difference between the reference signal P1 and the comparison signal P3 (S23).

  Next, the phase comparator 11 calculates a second set value based on the detected phase difference between the reference signal P1 and the comparison signal P3 (S24). The second set value is a value that determines the oscillation frequency of the oscillator 13. That is, when the second set value is set in the oscillator 13, the oscillator 13 outputs an oscillation signal P2 having an oscillation frequency corresponding to the second set value. The phase comparator 11 outputs a second control signal P4 corresponding to the second set value to the switch 16. That is, when the oscillator 13 acquires the second control signal P4 from the switcher 16, the oscillator 13 outputs an oscillation signal P2 having an oscillation frequency corresponding to the second set value.

Returning to FIG.
The switch 16 determines whether or not the phase difference between the reference signal P1 and the comparison signal P3 is larger than a predetermined phase difference (S3). The switch 16 is performed by comparing the magnitude of the second set value corresponding to the second control signal P4 acquired from the phase comparator 11 and the reference value, for example. That is, for example, when the second set value is larger than the reference value, the switch 16 determines that the phase difference between the reference signal P1 and the comparison signal P3 is larger than a predetermined phase difference. On the other hand, when the second set value is less than or equal to the reference value, the switch 16 determines that the phase difference between the reference signal P1 and the comparison signal P3 is less than or equal to a predetermined phase difference (the phase difference is not greater than the predetermined phase difference) Is determined.

  When it is determined that the phase difference between the reference signal P1 and the comparison signal P3 is larger than the predetermined phase difference (Yes in S3), the switch 16 sets the first set value in the oscillator 13 and the comparison counter. The count value is reset (S4). The comparison counter counts the comparison clock and generates a comparison signal P3.

  That is, the switch 16 outputs the first control signal P5 from the pulse width comparator 15 to the oscillator 13 as the control signal P6.

  In addition, the switch 16 outputs a reset signal P7 to the frequency divider 14. The reset signal P7 is a signal that resets the count value of the comparison counter. That is, when the frequency divider 14 acquires the reset signal P7, the frequency divider 14 resets the count value of the comparison counter, starts counting the comparison clock, and generates the comparison signal P3. As a result, the comparison signal P3 output from the frequency divider 14 has the same phase as the reference signal P1.

  When it is not determined that the phase difference between the reference signal P1 and the comparison signal P3 is larger than the predetermined phase difference (No in S3), the switch 16 sets the second set value in the oscillator 13 (S5).

  That is, the switch 16 outputs the second control signal P4 from the loop filter 12 to the oscillator 13 as the control signal P6.

  The oscillator 13 performs an oscillation process based on the first set value or the second set value (S6). That is, when the phase difference between the reference signal P1 and the comparison signal P3 is larger than a predetermined phase difference, the oscillator 13 calculates the pulse width of the reference signal P1 detected by the pulse width comparator 15 and the pulse width of the comparison signal P3. An oscillation signal P2 having an oscillation frequency determined according to the difference is output. On the other hand, when the phase difference between the reference signal P1 and the comparison signal P3 is not larger than the predetermined phase difference, the oscillator 13 is determined according to the phase difference between the reference signal P1 and the comparison signal P3 detected by the phase comparator 11. An oscillation signal P2 having the generated oscillation frequency is output.

  Here, as described above, when the phase difference between the reference signal P1 and the comparison signal P3 is larger than the predetermined phase difference, the pulse width of the comparison signal P3 output from the frequency divider 14 is the pulse width of the reference signal P1. (Or substantially the same, hereinafter the same). In other words, the first control signal P5 causes the oscillator 13 to output an oscillation signal P2 having an oscillation frequency such that the pulse width of the comparison signal P3 is the same as the pulse width of the reference signal P1.

  Further, as described above, when the phase difference between the reference signal P1 and the comparison signal P3 is larger than the predetermined phase difference, the count value of the comparison counter is reset, so that the comparison signal P3 output from the frequency divider 14 is The same phase as the reference signal P1.

  Thus, when the phase difference between the reference signal P1 and the comparison signal P3 is larger than the predetermined phase difference, the PLL circuit C1 makes the pulse width of the comparison signal P3 the same as the pulse width of the reference signal P1, The reference signal P1 and the comparison signal P3 are in phase.

FIG. 5 is a timing chart showing the relationship between the reference signal P1 and the comparison signal P3, where (a) is the reference signal P1 and (b) is the comparison signal P3.
This figure shows that there is no phase difference (the same phase) between the reference signal P1 of the cycle T11 and the comparison signal P3 of the cycle T21 until time t1. In the figure, after time t1, the cycle of the reference signal P1 changes from T11 to T12, and there is a difference between the pulse width of the reference signal P1 and the pulse width of the comparison signal P3. The reference signal P1 and the comparison signal P3 It shows that there is a phase difference between and.

FIG. 6 is a timing chart showing another relationship between the reference signal P1 and the comparison signal P3. (A) is the reference signal P1 and (b) is the comparison signal P3.
The figure shows that until time t2, there is a phase difference between the reference signal P1 of the cycle T12 and the comparison signal P3 of the cycle T21. In the figure, after time t2, the period of the comparison signal P3 changes from T21 to T22, the pulse width of the reference signal P1 and the pulse width of the comparison signal P3 match, and the reference signal P1 and the comparison signal P3 Indicates that no phase difference has occurred. This time t2 is the time when the frequency divider 14 acquires the reset signal P7 from the switch 16 and resets the comparison counter.

● Summary ●
According to the embodiment described above, when the phase difference between the reference signal P1 and the comparison signal P3 is larger than the predetermined phase difference, the PLL circuit C1 calculates the pulse width between the reference signal P1 and the comparison signal P3. An oscillation signal P2 having an oscillation frequency corresponding to the difference is output so that the pulse width of the reference signal P1 and the comparison signal P3 are the same, and the reference signal P1 and the comparison signal P3 are in phase. On the other hand, the PLL circuit C1 outputs an oscillation signal P2 having an oscillation frequency corresponding to the phase difference between the reference signal P1 and the comparison signal P3 when the phase difference between the reference signal P1 and the comparison signal P3 is not larger than a predetermined phase difference. To do.

  That is, when the phase difference between the reference signal P1 and the comparison signal P3 becomes large, the PLL circuit C1 makes the pulse widths of the reference signal P1 and the comparison signal P3 the same, and makes the reference signal P1 and the comparison signal P3 the same. By setting the phase, the transition time from the unlocked state to the locked state can be shortened. That is, the PLL circuit C1 realizes both high speed and stability.

● Signal processing device ●
Next, an embodiment of the signal processing apparatus according to the present invention will be described.
A signal processing apparatus according to the present invention includes a signal processing circuit that processes an input signal input from the outside, and a PLL circuit that generates a clock signal of the signal processing circuit. 2 is a PLL circuit according to the present invention described in (1).

  As described above, since the PLL circuit according to the present invention can realize both high speed and stability, the signal processing apparatus according to the present invention can output a signal synchronized with the input signal. it can.

  Examples of the signal processing device according to the present invention include a device that converts an analog signal into a digital signal.

● Summary of features of oscillation circuit and PLL circuit according to the present invention ●
The characteristics of the oscillation circuit and the PLL circuit according to the present invention described above are summarized below.

(Feature 1)
A pulse width comparator for detecting a difference between the pulse width of the reference signal input to the phase comparator of the PLL circuit and the pulse width of the comparison signal output from the oscillator of the PLL circuit and input to the phase comparator When,
A switch that causes the oscillator to input one of the signal from the phase comparator and the signal from the pulse width comparator;
With
The oscillator to which the signal from the pulse width comparator is input outputs an oscillation frequency signal determined based on the difference in pulse width detected by the pulse width comparator,
When the signal from the pulse width comparator is input to the oscillator, the reference signal and the comparison signal are in phase.
An oscillation circuit characterized by that.

(Feature 2)
The oscillator to which the signal from the pulse width comparator is input outputs a signal having the same pulse width as the pulse width of the reference signal.
The oscillation circuit according to Feature 1.

(Feature 3)
The comparison signal is generated by being counted by a comparison counter,
When the signal from the pulse width comparator is input to the oscillator, the count value of the comparison counter is reset.
The oscillation circuit according to Feature 1 or 2.

(Feature 4)
The signal output from the oscillator is divided and input to the phase comparator as the comparison signal.
The oscillation circuit according to Feature 1 or 2.

(Feature 5)
The switch determines a signal input to the oscillator based on a phase difference between the reference signal and the comparison signal;
The oscillation circuit according to Feature 1 or 2.

(Feature 6)
When the phase difference is larger than a reference value, the switch causes the signal from the pulse width comparator to be input to the oscillator.
The oscillation circuit according to Feature 5.

(Feature 7)
The switch causes the oscillator to input a signal from the phase comparator when the phase difference is a reference value or less.
The oscillation circuit according to Feature 5 or 6.

(Feature 8)
The pulse width comparator is
A first counter that measures a pulse width of the reference signal by detecting and counting a falling edge of the reference signal;
A second counter for measuring a pulse width of the comparison signal by detecting and counting a falling edge of the comparison signal;
A subtractor that detects a difference between a pulse width of the reference signal and a pulse width of the comparison signal based on a difference between a count value of the first counter and a count value of the second counter;
Comprising
The oscillation circuit according to Feature 1 or 2.

(Feature 9)
The subtractor detects a difference between a pulse width of the reference signal and a pulse width of the comparison signal by subtracting a count value of the first counter from a count value of the second counter;
9. The oscillation circuit according to feature 8.

(Feature 10)
The subtractor detects a difference between a pulse width of the reference signal and a pulse width of the comparison signal by subtracting a count value of the second counter from a count value of the first counter;
9. The oscillation circuit according to feature 8.

(Feature 11)
A phase comparator for detecting a phase difference between the reference signal and the comparison signal;
An oscillator that outputs a signal having an oscillation frequency determined based on the phase difference;
A PLL circuit comprising:
When the phase difference is a predetermined phase difference, a signal having an oscillation frequency determined based on a difference between the pulse width of the reference signal and the pulse width of the comparison signal is output from the oscillator, and the comparison with the reference signal is performed. An oscillation circuit that makes the signal in phase,
With
The oscillation circuit is the oscillation circuit according to any one of features 1 to 10.
A PLL circuit characterized by that.

C1 PLL circuit C2 Oscillation circuit P1 Reference signal P2 Oscillation signal P3 Comparison signal P4 Second control signal P5 First control signal P6 Control signal P7 Comparison signal comparison counter reset signal 11 Phase comparator 12 Loop filter 13 Oscillator 14 Divider 15 Pulse width comparator 16 Switch

Claims (10)

A pulse width comparator for detecting a difference between the pulse width of the reference signal input to the phase comparator of the PLL circuit and the pulse width of the comparison signal output from the oscillator of the PLL circuit and input to the phase comparator When,
A switch that causes the oscillator to input one of the signal from the phase comparator and the signal from the pulse width comparator;
With
The comparison signal is generated by being counted by a comparison counter,
The oscillator to which the signal from the pulse width comparator is input is an oscillation frequency signal determined based on the difference in pulse width detected by the pulse width comparator, and has the same pulse width as that of the reference signal. Output a width signal ,
When the signal from the pulse width comparator is input to the oscillator, the count value of the comparison counter is reset to make the reference signal and the comparison signal in phase.
An oscillation circuit characterized by that. The signal output from the oscillator is divided and input to the phase comparator as the comparison signal.
The oscillation circuit according to claim 1. The switch determines a signal input to the oscillator based on a phase difference between the reference signal and the comparison signal;
The oscillation circuit according to claim 1 or 2. When the phase difference is larger than a reference value, the switch causes the signal from the pulse width comparator to be input to the oscillator.
The oscillation circuit according to claim 3. The switch causes the oscillator to input a signal from the phase comparator when the phase difference is a reference value or less.
The oscillation circuit according to claim 3 or 4. The pulse width comparator is
A first counter that measures a pulse width of the reference signal by detecting and counting a falling edge of the reference signal;
A second counter for measuring a pulse width of the comparison signal by detecting and counting a falling edge of the comparison signal;
A subtractor that detects a difference between a pulse width of the reference signal and a pulse width of the comparison signal based on a difference between a count value of the first counter and a count value of the second counter;
Comprising
The oscillation circuit according to claim 1 or 2. The subtractor detects a difference between a pulse width of the reference signal and a pulse width of the comparison signal by subtracting a count value of the first counter from a count value of the second counter;
The oscillation circuit according to claim 6. The subtractor detects a difference between a pulse width of the reference signal and a pulse width of the comparison signal by subtracting a count value of the second counter from a count value of the first counter;
The oscillation circuit according to claim 6. A phase comparator for detecting a phase difference between the reference signal and the comparison signal;
An oscillator that outputs a signal having an oscillation frequency determined based on the phase difference;
A PLL circuit comprising:
When the phase difference is a predetermined phase difference, a signal having an oscillation frequency determined based on the difference between the pulse width of the reference signal and the pulse width of the comparison signal is output from the oscillator, and the comparison with the reference signal is performed. An oscillation circuit that makes the signal in phase,
With
The oscillation circuit is the oscillation circuit according to any one of claims 1 to 8.
A PLL circuit characterized by that. A signal processing circuit for processing an input signal;
A PLL circuit for generating a clock signal of the signal processing circuit;
Having
The PLL circuit is the PLL circuit according to claim 9,
A signal processing apparatus.

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