CN106998204A - Oscillating circuit, PLL circuit and signal processing apparatus - Google Patents
Oscillating circuit, PLL circuit and signal processing apparatus Download PDFInfo
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- CN106998204A CN106998204A CN201610833824.6A CN201610833824A CN106998204A CN 106998204 A CN106998204 A CN 106998204A CN 201610833824 A CN201610833824 A CN 201610833824A CN 106998204 A CN106998204 A CN 106998204A
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- 230000006641 stabilisation Effects 0.000 description 5
- 238000011105 stabilization Methods 0.000 description 5
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
- H03L7/102—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
Abstract
The present invention provides a kind of oscillating circuit for the high speed and stability that can realize PLL circuit simultaneously, it is characterised in that possess：Pwm comparator (15), it detects the difference for the pulse width that pulse width of the input to the reference signal (P1) of the phase comparator (11) of PLL circuit is exported with the oscillator (13) from PLL circuit and inputted to the comparison signal of phase comparator (P3)；And switch (16), it inputs either party in the signal from phase comparator and the signal from the pwm comparator to oscillator.Comparison signal is generated by comparing rolling counters forward.It has input the oscillator of the signal from pwm comparator, export in the signal for the frequency of oscillation that the difference of the pulse width detected based on pwm comparator is determined, there is the signal of same pulse width with the pulse width of reference signal.When signal from pwm comparator is inputted to oscillator, the count value for comparing counter is resetted so that reference signal is identical with the phase of comparison signal.
Description
Technical field
The present invention relates to a kind of oscillating circuit, PLL circuit and signal processing apparatus.
Background technology
PLL (Phase Locked Loop) loop is output and the electricity of the phase locked signal of the reference signal of input
Sub-loop.PLL circuit is made up of phase comparator, loop filter, oscillator and frequency divider.Phase comparator detects base
Calibration signal and the phase difference of the signal from frequency divider, the output error signal proportional with the phase difference detected.Return
Path filter is averaged to the error signal exported from phase comparator, the less direct current signal of output alternating component.Loop
Wave filter is such as low pass filter.Oscillator output is corresponding with the direct current signal (DC voltage) exported from loop filter
The signal of frequency.Frequency divider is divided to the signal exported from oscillator.(by feeding back) is transfused to by the signal of frequency dividing extremely
Phase comparator.
So, reference signal of the oscillator based on input to phase comparator by oscillator with being exported and by frequency divider point
The phase difference of the signal of frequency, exports the signal of the frequency of oscillation determined by loop filter.So, PLL circuit be in
Input the state exported to the phase locked signal of the reference signal of phase comparator from oscillator.The state is PLL circuit
Blocking.On the other hand, the released state of PLL circuit is, not with inputting to the phase of the reference signal of phase comparator
The state that synchronous signal is exported from oscillator.
PLL circuit is worked in the way of maintaining blocking.That is, PLL circuit is being solution from blocking transition
During lock status, start working using transition as blocking.That is, such as PLL circuit there occurs in the reference signal of input
When the phase of change etc., reference signal and the signal exported from oscillator deviation occurs and occurs phase difference, as released state.
Phase difference between the signal that PLL circuit as released state exports for elimination reference signal and from oscillator, it is defeated from oscillator
Go out the signal of the frequency of oscillation determined by loop filter, transition is blocking.
The stabilization time of PLL circuit is in the relation of shifting (Trade-off) with output jitter.Stabilization time is
Refer to, until the phase with reference signal has the time that the signal of same phase is exported from oscillator from reference signal input.
Output jitter is, the deviation in the cycle of reference signal and the signal exported from oscillator.Stabilization time and output jitter are depended on
The cut-off frequency of loop filter.That is, for shorten stabilization time and by the cut-off frequency of loop filter be set to compared with
Gao Shi, output jitter becomes big.That is, the frequency of the signal exported from oscillator is consistent with the frequency of reference signal for the time being.
The phase of signal of the reference signal with being exported from oscillator is identical.But afterwards, there is deviation and unstable in the phase of these signals
It is fixed.On the other hand, when the cut-off frequency of loop filter being set into relatively low to reduce output jitter, stabilization time is elongated.
That is, the frequency of the signal exported from oscillator slowly changes and consistent with the frequency of reference signal, keep afterwards
It is stable.In this case, it is necessary to realize the high speed and stability of PLL circuit simultaneously.
A kind of PLL circuit has been proposed so far, it possesses multiple loop filters, selection is with reference signal and from vibration
The corresponding loop filter of phase difference of the signal of device output (for example, referring to patent document 1).
Prior art literature
Patent document
Patent document 1：Japanese Patent Laid-Open 9-284132 publications
The content of the invention
Problems to be solved by the invention
If but in order to realize the high speed and stability of PLL circuit simultaneously, and exported with reference signal and from oscillator
The phase difference of signal correspond to possess multiple loop filters, can cause the structure of PLL circuit and become complicated.If moreover, correspondence
Switch multiple loop filters by stages in reference signal and the phase difference of signal exported from oscillator, when can cause to stablize
Between it is elongated.
The present invention is to solve above-mentioned prior art problem and complete, can be while realizing height its object is to provide one kind
The PLL circuit of speed and stability.
The solution used to solve the problem
The present invention solution be, a kind of oscillating circuit, it is characterised in that
Possess：
Pwm comparator, its detect input to PLL circuit phase comparator reference signal pulse width, with from
The difference for the pulse width that the oscillator of PLL circuit is exported and inputted to the comparison signal of phase comparator, and
Switch, it is by either party input in the signal from phase comparator and the signal from pwm comparator
To oscillator,
The oscillator of the signal from pwm comparator is have input, the pulse width detected based on pwm comparator is exported
Difference determine frequency of oscillation signal,
When signal from pwm comparator is inputted to oscillator, make reference signal identical with the phase of comparison signal.
The effect of invention
In accordance with the invention it is possible to realize high speed and stability simultaneously.
Brief description of the drawings
Fig. 1 is the oscillating circuit of the present invention and the block diagram of PLL circuit.
Fig. 2 is the flow chart of the signal transacting of Fig. 1 PLL circuit.
Fig. 3 compares the flow chart of processing for the pulse width of Fig. 1 PLL circuit.
The flow chart that Fig. 4 is handled for the phase bit comparison of Fig. 1 PLL circuit.
Fig. 5 is the time schedule figure for showing to input the relation to the reference signal of Fig. 1 PLL circuit and comparison signal.
Fig. 6 is the time schedule for showing to input other relations to the reference signal of Fig. 1 PLL circuit and comparison signal
Figure.
Description of reference numerals
C1 PLL circuits
C2 oscillating circuits
P1 reference signals
P2 oscillator signals
P3 comparison signals
The control signals of P4 the 2nd
The control signals of P5 the 1st
P6 control signals
P7 reset signals
11 phase comparators
12 loop filters
13 oscillators
14 frequency dividers
15 pwm comparators
16 switch
Embodiment
Below, referring to the drawings, the embodiment to the oscillating circuit of the present invention, PLL circuit and signal processing apparatus is carried out
Explanation.
● the structure of oscillating circuit and PLL circuit ●
Fig. 1 is the oscillating circuit of the present invention and the block diagram of PLL circuit.
The PLL circuit C1 of the present invention has：Phase comparator 11, loop filter 12, oscillator 13, frequency divider 14, sheet
The oscillating circuit C2 of invention.Oscillating circuit C2 has pwm comparator 15, switch 16.Oscillating circuit C2 constitutes PLL circuit C1
A part.
The phase that phase comparator 11, loop filter 12, oscillator 13, frequency divider 14 possess with existing PLL circuit
Together.That is, PLL circuit C1 is different from existing PLL circuit on this point of possessing oscillating circuit C2.
Phase comparator 11 detect from external equipment (not shown) input reference signal P1, with from frequency divider 14 export
Comparison signal P3 phase difference, the output error signal proportional with the phase difference detected.
Reference signal P1, to 27MHz reference clock once count and generates for example, by each cycle.
Comparison signal P3, to 54MHz comparison clock once count and generates for example, by each two cycle.
12 pairs of error signals exported from phase comparator 11 of loop filter are averaged, and output alternating component is less
2nd control signal P4 of direct current.On the 2nd control signal P4, referring to aftermentioned content.
Oscillator 13 exports the oscillator signal P2 of frequency corresponding with the control signal P6 exported by switch 16.On control
Signal P6 processed.Referring to aftermentioned content.
The oscillator signal P2 that 14 pairs of frequency divider is exported by oscillator 13 is divided, output comparison signal P3.Comparison signal
P3 is inputted to phase comparator 11 and pwm comparator 15.
The pulse width of the detection reference signal of pwm comparator 15 P1 pulse width and comparison signal P3 pulse width
Difference, the output 1st control signal P5 proportional with the difference of pulse width detected.On the 1st control signal
P5, referring to aftermentioned content.
Pwm comparator 15 possesses：1st counter, the 2nd counter, subtracter.
1st counter is detected and counted by the trailing edge to reference signal P1, determines reference signal P1 pulse
Width.
2nd counter is detected and counted by the trailing edge to comparison signal P3, determines comparison signal P3 pulse
Width.
The difference of count value of the subtracter based on the 1st counter and the count value of the 2nd counter, calculates reference signal P1's
The difference of pulse width and comparison signal P3 pulse width.That is, for example, subtracter passes through the meter from the 2nd counter
Numerical value subtracts the count value of the 1st counter, or subtracts the count value of the 2nd counter from the count value of the 1st counter, calculates base
The difference of calibration signal P1 pulse width and comparison signal P3 pulse width.
The count value of 1st counter and the count value of the 2nd counter, are counted for example, by 27MHz measure with clock
Number.
2nd control signal P4 of switch self-loop wave filter in 16 future 12 and the 1st control from pwm comparator 15
Either party in signal P5 is inputted to oscillator 13.Phase difference of the switch 16 based on reference signal P1 Yu comparison signal P3,
By input to oscillator 13 signal deciding be the 2nd control signal P4 and the 1st control signal P5 in either party.Namely
Say, for example, switch 16 on the basis of reference signal P1 and comparison signal P3 phase difference when being worth following, by the 2nd control signal
P4 is inputted to oscillator 13；When the phase difference is more than a reference value, the 1st control signal P5 is inputted to oscillator 13.Namely
Say, when being worth following on the basis of reference signal P1 and comparison signal P3 phase difference, control signal P6 is the 2nd control signal P4.
On the other hand, when reference signal P1 and comparison signal P3 phase difference is more than a reference value, control signal P6 is the 1st control signal
P5.Switch 16 is used for a reference value for selecting the 2nd control signal P4 and the 1st control signal P5, is set in advance in switch 16.
The 2nd control signal P4 oscillator 13 is have input, it is phase difference corresponding to reference signal P1 and comparison signal P3, defeated
Go out the oscillator signal P2 of the frequency of oscillation determined by loop filter 12.The frequency of oscillation determined by loop filter 12 is to subtract
Go the value of reference signal P1 and comparison signal P3 phase difference.
The 1st control signal P5 oscillator 13 is have input, the pulse width based on reference signal P1 is with comparison signal P3's
The difference of pulse width, exports the oscillator signal P2 of the frequency of oscillation determined by pwm comparator 15.Determined by pwm comparator 15
Fixed frequency of oscillation is the value of the pulse width and the difference of comparison signal P3 pulse width that subtract reference signal P1.
That is, pwm comparator 15 remains the difference of pulse width and the corresponding relation of frequency of oscillation, based on this
Corresponding relation, is determined corresponding with the reference signal P1 pulse width and the difference of comparison signal P3 pulse width detected
Frequency of oscillation (the 1st setting value described later).
● the work of oscillating circuit and PLL circuit ●
Fig. 2 is the flow chart of PLL circuit C1 signal transacting.
During input reference signal P1 and comparison signal P3, PLL circuit C1 implement pulse width compare processing (S1) and
Phase bit comparison handles (S2).
Fig. 3 is the flow chart that pulse width compares processing (S1).
Pwm comparator 15 is after reference signal P1 (S11) is obtained, and the pulse using the 1st counter to reference signal P1 is wide
Degree (S13) is counted (measure).Similarly, pwm comparator 15 is counted after comparison signal P3 (S12) is obtained using the 2nd
Device is counted to comparison signal P3 pulse width (S14).
Then, the difference of the detection reference signal of pwm comparator 15 P1 pulse width and comparison signal P3 pulse width
(S15).The difference of pulse width detects (calculating) by the subtracter of pwm comparator 15.The subtracter profit of pwm comparator 15
The difference of pulse width is detected with the count value of the 1st counter and the count value of the 2nd counter.That is, subtracter passes through
The count value of the 1st counter is subtracted from the count value of the 2nd counter, or the 2nd counter is subtracted from the count value of the 1st counter
Count value, calculate the difference of reference signal P1 pulse width and comparison signal P3 pulse width.
Then, pulse width of the pwm comparator 15 based on the reference signal P1 calculated by subtracter is with comparison signal P3's
The difference of pulse width, calculates the 1st setting value (S16).1st setting value is the value for the frequency of oscillation for determining oscillator 13.Also
It is to say, sets the oscillator 13 of the 1st setting value, exports the oscillator signal P2 of frequency of oscillation corresponding with the 1st setting value.Pulsewidth
Comparator 15 exports 1st control signal P5 corresponding with the 1st setting value to switch 16.That is, oscillator 13 is from cutting
Parallel operation 16 is obtained after the 1st control signal P5, exports the oscillator signal P2 of frequency of oscillation corresponding with the 1st setting value.
Fig. 4 is the flow chart that phase bit comparison handles (S2).
Phase comparator 11 obtain reference signal P1 and comparison signal P3 (S21, S22) after, detection reference signal P1 with
Comparison signal P3 phase difference (S23).
Then, phase comparator 1 is calculated the 2nd and set based on the reference signal P1 detected and comparison signal P3 phase difference
Definite value (S24).2nd setting value is the value for the frequency of oscillation for determining oscillator 13.That is, setting shaking for the 2nd setting value
Device 13 is swung, the oscillator signal P2 of frequency of oscillation corresponding with the 2nd setting value is exported.Phase comparator 11 will be with the 2nd setting value pair
The 2nd control signal P4 answered is exported to switch 16.That is, oscillator 13 obtains the 2nd control signal P4 from switch 16
Afterwards, the oscillator signal P2 of frequency of oscillation corresponding with the 2nd setting value is exported.
Return to Fig. 2.
Switch 16 is judged whether reference signal P1 and comparison signal P3 phase difference is more than defined phase difference
(S3).Switch 16 for example passes through pair the 2nd setting value corresponding with the 2nd control signal P4 obtained from phase comparator 11 and a base
The size of quasi- value is compared and implements to judge.That is, for example, when the 2nd setting value is more than a reference value, switch 16 is sentenced
The phase difference for determining reference signal P1 and comparison signal P3 is more than defined phase difference.On the other hand, it is worth on the basis of the 2nd setting value
When following, the determinating reference signal P1 of switch 16 and comparison signal P3 phase difference is (phase difference below defined phase difference
No more than defined phase difference).
When determinating reference signal P1 and comparison signal P3 phase difference is more than defined phase difference (S3 Yes), switching
Device 16 by the 1st setting value while oscillator 13 are set in, and the comparison possessed to frequency divider 14 handles the counting of counter
Value is resetted (S4).Compare counter to count comparison clock, generation comparison signal P3.
That is, switch 16 is exported the 1st control signal P5 from pwm comparator 15 as control signal P6
To oscillator 13.
In addition, switch 16 exports reset signal P7 to frequency divider 14.Reset signal P7 is the meter to comparing counter
The signal that numerical value is resetted.That is, frequency divider 14 is obtained after reset signal P7, the count value for comparing counter is carried out
Reset, start the counting of comparison clock, generation comparison signal P3.So, from frequency divider 14 export comparison signal P3 with
Reference signal P1 phase is identical.
When non-determinating reference signal P1 and comparison signal P3 phase difference is more than defined phase difference (S3 No), switching
2nd setting value is set in oscillator 13 (S5) by device 16.
That is, switch 16 is defeated as control signal P6 using the 2nd control signal P4 for coming from loop filter 12
Go out to oscillator 13.
Oscillator 13 is based on the 1st setting value or the 2nd setting value, implements oscillation treatment (S6).That is, working as reference signal
When P1 and comparison signal P3 phase difference are more than defined phase difference, oscillator 13 is exported based on being detected by pwm comparator 15
The oscillator signal P2 for the frequency of oscillation that the difference of reference signal P1 pulse width and comparison signal P3 pulse width is determined.Separately
On the one hand, when reference signal P1 and comparison signal P3 phase difference is not more than defined phase difference, the output of oscillator 13 is based on
The oscillator signal P2 for the frequency of oscillation that the reference signal P1 detected by phase comparator 11 and comparison signal P3 phase difference is determined.
Herein, as it was previously stated, when reference signal P1 and comparison signal P3 phase difference are more than defined phase difference, from point
Pulse width (or roughly the same, the letter below identical with reference signal P1 pulse width for the comparison signal P3 that frequency device 14 is exported
Claim " identical ").In other words, the 1st control signal P5 exports oscillator signal P2 to oscillator 13, wherein, oscillator signal P2's
Frequency of oscillation is the pulse width for making comparison signal P3 with reference signal P1 pulse width identical frequency of oscillation.
In addition, as it was previously stated, when reference signal P1 and comparison signal P3 phase difference are more than defined phase difference, due to
The count value for comparing counter is reset, and the comparison signal P3 exported from frequency divider 14 is identical with reference signal P1 phase.
So, when reference signal P1 and comparison signal P3 phase difference is more than defined phase difference, PLL circuit C1 makes
While comparison signal P3 pulse width is identical with reference signal P1 pulse width, also make reference signal P1 and comparison signal
P3 phase is identical.
Fig. 5 is the time schedule figure for the relation for showing reference signal P1 and comparison signal P3, signal P1, (b) on the basis of (a)
For comparison signal P3.
The figure shows before time tl, the reference signal P1 of cycle T 11 is not produced with the comparison signal P3 of cycle T 21
Phase difference (phase is identical).Shown in the figure, after time tl, reference signal P1 cycle is changed into T12, benchmark letter from T11
Number P1 pulse width generates difference with comparison signal P3 pulse width, and reference signal P1 generates phase with comparison signal P3
Potential difference.
Fig. 6 is the time schedule figure for other relations for showing reference signal P1 and comparison signal P3, signal on the basis of (a)
P1, (b) is comparison signal P3.
The figure shows before moment t2, the reference signal P1 of cycle T 12 is generated with the comparison signal P3 of cycle T 21
Phase difference.The figure shows after moment t2, comparison signal P3 cycle is changed into T22 from T21, and reference signal P1 pulse is wide
Degree is consistent with comparison signal P3 pulse width, and reference signal P1 and comparison signal P3 does not produce phase difference.Moment t2 is to divide
Frequency device 14 obtains reset signal P7 from switch 16, at the time of reset to comparing counter.
● summarize ●
Embodiment from the description above, PLL circuit C1 is more than in reference signal P1 and comparison signal P3 phase difference
During defined phase difference, the difference for exporting the pulse width with reference signal P1 pulse width and comparison signal P3 corresponding is shaken
Swing the oscillator signal P2 of frequency, make reference signal P1 pulse width it is identical with comparison signal P3 pulse width while,
Make reference signal P1 identical with comparison signal P3 phase.On the other hand, PLL circuit C1 is in reference signal P1 and comparison signal P3
Phase difference be not more than as defined in phase difference when, export corresponding with reference signal P1 and comparison signal P3 phase difference oscillation frequency
The oscillator signal P2 of rate.
That is, PLL circuit C1 makes reference signal when reference signal P1 and comparison signal P3 phase difference variable is big
While P1 is identical with comparison signal P3 pulse width, makes reference signal P1 identical with comparison signal P3 phase, accordingly can
It is enough to shorten the time for switching to blocking from released state.That is, PLL circuit C1 can realize high speed and stably simultaneously
Property.
● signal processing apparatus ●
Below, the embodiment to the signal processing apparatus of the present invention is illustrated.
The signal processing apparatus of the present invention possesses：Signal processing circuit, it handles the input signal from outside input；PLL
Circuit, it generates the clock signal of the signal processing circuit.The PLL circuit is PLL electricity of the invention described as indicated above
Road.
As described in the foregoing description, PLL circuit of the invention can realize high speed and stability simultaneously, therefore, the present invention
Signal processing apparatus can export the signal synchronous with input signal.
Moreover, the example of the signal processing apparatus as the present invention, such as have and convert analog signals into data signal
Device etc..
● oscillating circuit of the invention and the feature of PLL circuit are summarized ●
On oscillating circuit of the invention as described in the foregoing description and the feature of PLL circuit, summarize as follows.
(feature 1)
A kind of oscillating circuit, it is characterised in that
Possess：
Pwm comparator, its detect input to the reference signal of the phase comparator of PLL circuit pulse width with from institute
The difference of the pulse width for the comparison signal that the oscillator of PLL circuit is exported and inputted to the phase comparator is stated, and
Switch, it will be any in the signal from the phase comparator and the signal from the pwm comparator
One side is inputted to the oscillator,
The comparison signal is generated by comparing rolling counters forward,
The oscillator of the signal from the pwm comparator is have input, output is examined based on the pwm comparator
Pulse width in the signal for the frequency of oscillation that the difference of the pulse width of survey is determined with the reference signal has identical pulse
The signal of width,
When signal from the pwm comparator is inputted to the oscillator, the count value for comparing counter is entered
Row is resetted so that the reference signal is identical with the phase of the comparison signal.
(feature 2)
Oscillating circuit according to feature 1, it is characterised in that
The signal exported from the oscillator is divided and inputted as the comparison signal to the phase comparator.
(feature 3)
Oscillating circuit according to feature 1 or 2, it is characterised in that
Phase difference of the switch based on the reference signal and the comparison signal determines input to the oscillator
Signal.
(feature 4)
Oscillating circuit according to feature 3, it is characterised in that
The switch inputs the signal from the pwm comparator to institute when the phase difference is more than a reference value
State oscillator.
(feature 5)
Oscillating circuit according to feature 3 or 4, it is characterised in that
The switch when being worth following on the basis of the phase difference, by the signal from the phase comparator input to
The oscillator.
(feature 6)
Oscillating circuit according to feature 1 or 2, it is characterised in that
The pwm comparator possesses：
1st counter, it is detected and counted by the trailing edge to the reference signal, determines the reference signal
Pulse width；
2nd counter, it is detected and counted by the trailing edge to the comparison signal, determines the comparison signal
Pulse width；And
Subtracter, the difference of its count value and the count value of the 2nd counter based on the 1st counter, detection
The difference of the pulse width of the reference signal and the pulse width of the comparison signal.
(feature 7)
Oscillating circuit according to feature 6, it is characterised in that
The subtracter detects institute by subtracting the count value of the 1st counter from the count value of the 2nd counter
State the difference of the pulse width of reference signal and the pulse width of the comparison signal.
(feature 8)
Oscillating circuit according to feature 6, it is characterised in that
The subtracter detects institute by subtracting the count value of the 2nd counter from the count value of the 1st counter
State the difference of the pulse width of reference signal and the pulse width of the comparison signal.
(feature 9)
A kind of PLL circuit, has：Detect the phase comparator of the phase difference of reference signal and comparison signal, and output base
The oscillator of the signal of the frequency of oscillation determined in the phase difference,
Characterized in that,
Possess：Oscillating circuit, it is when the phase difference is defined phase difference, from oscillator output based on described
The signal for the frequency of oscillation that the difference of the pulse width of reference signal and the pulse width of the comparison signal is determined, makes the base
Calibration signal is identical with the phase of the comparison signal,
The oscillating circuit is, the oscillating circuit described in any one of feature 1 to 8.
Claims (10)
1. a kind of oscillating circuit, it is characterised in that
Possess：
Pwm comparator, its detect input to the reference signal of the phase comparator of PLL circuit pulse width with from the PLL
The difference of the pulse width for the comparison signal that the oscillator of circuit is exported and inputted to the phase comparator, and
Switch, it is by either party in the signal from the phase comparator and the signal from the pwm comparator
Input to the oscillator,
The comparison signal is generated by comparing rolling counters forward,
The oscillator of the signal from the pwm comparator is have input, what output was detected based on the pwm comparator
Pulse width in the signal for the frequency of oscillation that the difference of pulse width is determined with the reference signal has same pulse width
Signal,
When signal from the pwm comparator is inputted to the oscillator, the count value for comparing counter is answered
Position is so that the reference signal is identical with the phase of the comparison signal.
2. oscillating circuit according to claim 1, it is characterised in that
The signal exported from the oscillator is divided and inputted as the comparison signal to the phase comparator.
3. oscillating circuit according to claim 1 or 2, it is characterised in that
Phase difference of the switch based on the reference signal and the comparison signal determines input to the letter of the oscillator
Number.
4. oscillating circuit according to claim 3, it is characterised in that
Signal from the pwm comparator is inputted to described and shaken when the phase difference is more than a reference value by the switch
Swing device.
5. the oscillating circuit according to claim 3 or 4, it is characterised in that
The switch inputs the signal from the phase comparator to described when being worth following on the basis of the phase difference
Oscillator.
6. oscillating circuit according to claim 1 or 2, it is characterised in that
The pwm comparator possesses：
1st counter, it is detected and counted by the trailing edge to the reference signal, determines the arteries and veins of the reference signal
Rush width,
2nd counter, it is detected and counted by the trailing edge to the comparison signal, determines the arteries and veins of the comparison signal
Width is rushed, and
Subtracter, the difference of its count value and the count value of the 2nd counter based on the 1st counter, detection is described
The difference of the pulse width of reference signal and the pulse width of the comparison signal.
7. oscillating circuit according to claim 6, it is characterised in that
The subtracter detects the base by subtracting the count value of the 1st counter from the count value of the 2nd counter
The difference of the pulse width of calibration signal and the pulse width of the comparison signal.
8. oscillating circuit according to claim 6, it is characterised in that
The subtracter detects the base by subtracting the count value of the 2nd counter from the count value of the 1st counter
The difference of the pulse width of calibration signal and the pulse width of the comparison signal.
9. a kind of PLL circuit, has：Detect that the phase comparator of the phase difference of reference signal and comparison signal, and output are based on
The oscillator of the signal for the frequency of oscillation that the phase difference is determined, it is characterised in that
Possess：Oscillating circuit, it is based on the benchmark when the phase difference is defined phase difference from oscillator output
The signal for the frequency of oscillation that the difference of the pulse width of signal and the pulse width of the comparison signal is determined, believes the benchmark
It is number identical with the phase of the comparison signal,
The oscillating circuit is, the oscillating circuit described in any one of claim 1 to 8.
10. a kind of signal processing apparatus, it is characterised in that
Have：
Signal processing circuit, it handles the signal of input, and
PLL circuit, it generates the clock signal of the signal processing circuit,
The PLL circuit is the PLL circuit described in claim 9.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015230181A JP5883984B1 (en) | 2015-11-26 | 2015-11-26 | Oscillation circuit, PLL circuit, and signal processing device |
| JP2015-230181 | 2015-11-26 |
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| Publication Number | Publication Date |
|---|---|
| CN106998204A true CN106998204A (en) | 2017-08-01 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610833824.6A Pending CN106998204A (en) | 2015-11-26 | 2016-09-20 | Oscillating circuit, PLL circuit and signal processing apparatus |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP5883984B1 (en) |
| KR (1) | KR101716411B1 (en) |
| CN (1) | CN106998204A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107835013A (en) * | 2017-12-08 | 2018-03-23 | 成都前锋电子仪器有限责任公司 | A kind of timing circuit for pulse pattern generator |
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| US7541848B1 (en) * | 2007-12-25 | 2009-06-02 | Hitachi, Ltd. | PLL circuit |
| CN102332911A (en) * | 2010-05-24 | 2012-01-25 | 松下电器产业株式会社 | PLL circuit for reducing reference leak and phase noise |
| JP2013197692A (en) * | 2012-03-16 | 2013-09-30 | Yokogawa Electric Corp | Pll clock generation circuit |
| JP2013223075A (en) * | 2012-04-16 | 2013-10-28 | Lapis Semiconductor Co Ltd | Pll frequency synthesizer, semiconductor integrated device and radio communication equipment |
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| JPS5784625A (en) * | 1980-11-17 | 1982-05-27 | Fujitsu Ltd | Phase synchronizing oscillator |
| JPS61167222A (en) * | 1985-01-21 | 1986-07-28 | Hitachi Ltd | Phase locked loop |
| JPS6278917A (en) * | 1985-10-02 | 1987-04-11 | Hitachi Ltd | Phase locked loop circuit |
| JPH0235538U (en) * | 1988-08-30 | 1990-03-07 | ||
| JPH09284132A (en) | 1996-04-15 | 1997-10-31 | Matsushita Electric Ind Co Ltd | Pll circuit |
| JP3308846B2 (en) * | 1997-03-14 | 2002-07-29 | 株式会社東芝 | Phase synchronization circuit and recording / reproducing device |
| JP4519746B2 (en) * | 2005-09-22 | 2010-08-04 | ローム株式会社 | Clock generation circuit and electronic device equipped with the same |
| JP5722733B2 (en) * | 2011-09-12 | 2015-05-27 | 新日本無線株式会社 | PLL circuit and calibration method thereof |
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2015
- 2015-11-26 JP JP2015230181A patent/JP5883984B1/en active Active
-
2016
- 2016-06-29 KR KR1020160081951A patent/KR101716411B1/en active IP Right Grant
- 2016-09-20 CN CN201610833824.6A patent/CN106998204A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7541848B1 (en) * | 2007-12-25 | 2009-06-02 | Hitachi, Ltd. | PLL circuit |
| CN102332911A (en) * | 2010-05-24 | 2012-01-25 | 松下电器产业株式会社 | PLL circuit for reducing reference leak and phase noise |
| JP2013197692A (en) * | 2012-03-16 | 2013-09-30 | Yokogawa Electric Corp | Pll clock generation circuit |
| JP2013223075A (en) * | 2012-04-16 | 2013-10-28 | Lapis Semiconductor Co Ltd | Pll frequency synthesizer, semiconductor integrated device and radio communication equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107835013A (en) * | 2017-12-08 | 2018-03-23 | 成都前锋电子仪器有限责任公司 | A kind of timing circuit for pulse pattern generator |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101716411B1 (en) | 2017-03-14 |
| JP5883984B1 (en) | 2016-03-15 |
| JP2017098799A (en) | 2017-06-01 |
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