JPH0235538U - - Google Patents
Info
- Publication number
- JPH0235538U JPH0235538U JP11285788U JP11285788U JPH0235538U JP H0235538 U JPH0235538 U JP H0235538U JP 11285788 U JP11285788 U JP 11285788U JP 11285788 U JP11285788 U JP 11285788U JP H0235538 U JPH0235538 U JP H0235538U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- circuit
- state
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 5
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案のクレーム対応図、第２図は本
考案のＰＬＬ回路の一実施例を示すブロツク図（
一部回路で示す）、第３図は第２図における本考
案の動作を説明する波形図、第４図は従来のＰＬ
Ｌ回路を示すブロツク図である。
１，９…位相比較回路、３，１９…ループフイ
ルタ（積分回路）、５，２１…発振回路（ＶＣＯ
）、７，１１…分周回路、１３…位相差判別回路
、１５…補正信号発生回路、１７…切換回路、２
３…パルス幅変換回路、２５…パルス幅位相比較
回路、２７，３３，３５…インバータ、２９…Ａ
ＮＤ回路、３１…スリー・ステート・バツフア、
Ｃ１〜Ｃ５…コンデンサ、Ｄ１，Ｄ２…可変容量
ダイオード、Ｒ１〜Ｒ５…抵抗。
Fig. 1 is a diagram corresponding to the claims of the present invention, and Fig. 2 is a block diagram showing an embodiment of the PLL circuit of the present invention.
3 is a waveform diagram explaining the operation of the present invention in FIG. 2, and FIG. 4 is a waveform diagram of the conventional PL
FIG. 3 is a block diagram showing an L circuit. 1, 9... Phase comparison circuit, 3, 19... Loop filter (integrator circuit), 5, 21... Oscillation circuit (VCO
), 7, 11... Frequency dividing circuit, 13... Phase difference discrimination circuit, 15... Correction signal generation circuit, 17... Switching circuit, 2
3...Pulse width conversion circuit, 25...Pulse width phase comparison circuit, 27, 33, 35...Inverter, 29...A
ND circuit, 31...three-state buffer,
C1 to C5 ...capacitor, D1 , D2 ...variable capacitance diode, R1 to R5 ...resistance.
Claims (1)
号を出力する位相比較回路と、 入力発振信号を分周して前記分周信号を出力す
る分周回路と、 前記基準信号に対して前記分周信号が所定量の
位相差範囲内にある第１の状態と前記位相差範囲
外にある第２の状態とを判別して判別信号を出力
する位相差判別回路と、 補正信号を発生する補正信号発生回路と、 前記判別信号によつて前記第１の状態では前記
誤差信号を、前記第２の状態では前記補正信号を
選択的に切換え出力する切換回路と、 前記誤差信号および前記補正信号から制御信号
を出力するループフイルタと、 前記制御信号のレベルに応じた周波数の前記発
振信号を前記分周回路へ出力するとともに、前記
分周信号が前記第１の状態であつて前記基準信号
と一定量の位相差となる周波数の前記発振信号を
出力するように制御された発振回路と、 を具備してなり、 前記補正信号発生回路は、前記分周信号によつ
て前記第１の状態となり得る周波数の前記補正信
号を発生するよう構成されてなることを特徴とす
るＰＬＬ回路。[Claims for Utility Model Registration] A phase comparator circuit that outputs an error signal according to the phase difference between a reference signal and a frequency-divided signal, and a frequency divider circuit that divides an input oscillation signal and outputs the frequency-divided signal. , phase difference discrimination for discriminating between a first state in which the frequency-divided signal is within a predetermined amount of phase difference range with respect to the reference signal and a second state in which it is outside the phase difference range and outputting a discrimination signal; a correction signal generation circuit that generates a correction signal; and a switching circuit that selectively switches and outputs the error signal in the first state and the correction signal in the second state according to the discrimination signal. , a loop filter that outputs a control signal from the error signal and the correction signal; and a loop filter that outputs the oscillation signal of a frequency corresponding to the level of the control signal to the frequency dividing circuit, and that the frequency divided signal is an oscillation circuit that is controlled to output the oscillation signal at a frequency that has a certain amount of phase difference from the reference signal in the state of A PLL circuit characterized in that the PLL circuit is configured to generate the correction signal at a frequency that can be in the first state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11285788U JPH0235538U (en) | 1988-08-30 | 1988-08-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11285788U JPH0235538U (en) | 1988-08-30 | 1988-08-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0235538U true JPH0235538U (en) | 1990-03-07 |
Family
ID=31352175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11285788U Pending JPH0235538U (en) | 1988-08-30 | 1988-08-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0235538U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5883984B1 (en) * | 2015-11-26 | 2016-03-15 | イメージニクス株式会社 | Oscillation circuit, PLL circuit, and signal processing device |
-
1988
- 1988-08-30 JP JP11285788U patent/JPH0235538U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5883984B1 (en) * | 2015-11-26 | 2016-03-15 | イメージニクス株式会社 | Oscillation circuit, PLL circuit, and signal processing device |
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