JPH0298527U - - Google Patents
Info
- Publication number
- JPH0298527U JPH0298527U JP709889U JP709889U JPH0298527U JP H0298527 U JPH0298527 U JP H0298527U JP 709889 U JP709889 U JP 709889U JP 709889 U JP709889 U JP 709889U JP H0298527 U JPH0298527 U JP H0298527U
- Authority
- JP
- Japan
- Prior art keywords
- basic clock
- clock pulse
- input signal
- phase
- phase difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の一実施例によるクロツク位相
制御回路の構成図、第２図ないし第５図は同実施
例の動作を説明するためのタイミングチヤートで
ある。
１１……第１フリツプフロツプ、１２……第２
フリツプフロツプ、１３，１４，１８……インバ
ータ、１５〜１７，１９……ナンド回路。
FIG. 1 is a block diagram of a clock phase control circuit according to an embodiment of the present invention, and FIGS. 2 to 5 are timing charts for explaining the operation of the embodiment. 11...first flip-flop, 12...second flip-flop
Flip-flop, 13, 14, 18...inverter, 15-17, 19... NAND circuit.
Claims (1)
基本クロツク作成部により作成された基本クロツ
クパルスの周波数の整数分の１の周波数に設定さ
れた入力信号と、この入力信号と上記基本クロツ
クパルスとの位相関係を検出する位相検出手段と
、この手段により検出された上記入力信号と基本
クロツクパルスとの位相差が設定値以下の時は上
記基本クロツクパルスをそのままの位相で出力し
、上記入力信号と基本クロツクパルスとの位相差
が設定値より大きくなつた時に上記基本クロツク
パルスを反転して出力する手段とを具備したこと
を特徴とするクロツク位相制御回路。 A basic clock generation section including a PLL circuit, an input signal set to a frequency that is an integer fraction of the frequency of the basic clock pulse generated by this basic clock generation section, and a phase relationship between this input signal and the basic clock pulse. When the phase difference between the input signal detected by the phase detection means and the basic clock pulse is less than the set value, the basic clock pulse is output with the same phase, and the phase difference between the input signal and the basic clock pulse is changed. A clock phase control circuit comprising means for inverting and outputting the basic clock pulse when the phase difference becomes larger than a set value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP709889U JPH0298527U (en) | 1989-01-25 | 1989-01-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP709889U JPH0298527U (en) | 1989-01-25 | 1989-01-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0298527U true JPH0298527U (en) | 1990-08-06 |
Family
ID=31211828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP709889U Pending JPH0298527U (en) | 1989-01-25 | 1989-01-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0298527U (en) |
-
1989
- 1989-01-25 JP JP709889U patent/JPH0298527U/ja active Pending
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