JPH0322431U - - Google Patents
Info
- Publication number
- JPH0322431U JPH0322431U JP8263989U JP8263989U JPH0322431U JP H0322431 U JPH0322431 U JP H0322431U JP 8263989 U JP8263989 U JP 8263989U JP 8263989 U JP8263989 U JP 8263989U JP H0322431 U JPH0322431 U JP H0322431U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock
- phase
- series
- phase shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010363 phase shift Effects 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図ないし第４図は本考案の実施例を示すも
ので、第１図は６相クロツク発生回路に実施した
場合の例を示すブロツク図、第２図は基本となる
の移相回路の構成を示すブロツク図、第３図は動
作を説明するためのタイミングチヤート、第４図
はｎ相クロツク発生回路の構成を示すブロツク図
、第５図は第４図のｎ相クロツク発生回路に対す
るタイミングチヤート、第６図は従来のｎ相クロ
ツク発生回路の動作を説明するためのタイミング
チヤートである。
１１……端子、１２ａ〜１２ｆ，１２１〜１２
ｎ……移相回路、２１……積分回路、２２……シ
ユミツトトリガ回路、２３……インバータ回路。
Figures 1 to 4 show examples of the present invention. Figure 1 is a block diagram showing an example of implementation in a six-phase clock generation circuit, and Figure 2 is a block diagram of the basic phase shift circuit. A block diagram showing the configuration, FIG. 3 is a timing chart for explaining the operation, FIG. 4 is a block diagram showing the configuration of the n-phase clock generation circuit, and FIG. 5 shows the timing for the n-phase clock generation circuit in FIG. 4. FIG. 6 is a timing chart for explaining the operation of a conventional n-phase clock generation circuit. 11...Terminal, 12a to 12f, 12 1 to 12
n ...phase shift circuit, 21...integrator circuit, 22...schmitt trigger circuit, 23...inverter circuit.
Claims (1)
回路を直列に接続してなる移相回路と、所望する
クロツク相数に応じて前記移相回路を直列に接続
し、該直列接続された移相回路の初段に原発振信
号を入力して順次位相遅延された信号をクロツク
パルスとして出力するクロツクパルス出力手段と
を具備したことを特徴とするｎ相クロツク発生回
路。 A phase shift circuit formed by connecting an integrator circuit, a Schmitt trigger circuit, and an inverter circuit in series is connected in series with the phase shift circuit according to the desired number of clock phases. 1. An n-phase clock generation circuit comprising clock pulse output means for inputting an oscillation signal and outputting sequentially phase-delayed signals as clock pulses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8263989U JPH0322431U (en) | 1989-07-13 | 1989-07-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8263989U JPH0322431U (en) | 1989-07-13 | 1989-07-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0322431U true JPH0322431U (en) | 1991-03-07 |
Family
ID=31629634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8263989U Pending JPH0322431U (en) | 1989-07-13 | 1989-07-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0322431U (en) |
-
1989
- 1989-07-13 JP JP8263989U patent/JPH0322431U/ja active Pending