JPS6157632U - - Google Patents

Info

Publication number
JPS6157632U
JPS6157632U JP14009884U JP14009884U JPS6157632U JP S6157632 U JPS6157632 U JP S6157632U JP 14009884 U JP14009884 U JP 14009884U JP 14009884 U JP14009884 U JP 14009884U JP S6157632 U JPS6157632 U JP S6157632U
Authority
JP
Japan
Prior art keywords
clock pulse
state
flip
change
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14009884U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14009884U priority Critical patent/JPS6157632U/ja
Publication of JPS6157632U publication Critical patent/JPS6157632U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す結線図、第2
図は第1図の各部の波形を示す図である。 図中、1は3分周部、2,3及び5は第1,第
2及び第3のフリツプフロツプ、6はアンド回路
(検出手段)である。
Figure 1 is a wiring diagram showing one embodiment of the present invention, Figure 2 is a wiring diagram showing an embodiment of the present invention.
The figure is a diagram showing waveforms at various parts in FIG. 1. In the figure, 1 is a frequency divider, 2, 3 and 5 are first, second and third flip-flops, and 6 is an AND circuit (detection means).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 少なくとも第1及び第2のフリツプフロツプに
より構成され異なる3つの状態をクロツクパルス
に同期して順次繰返し形成する少なくとも2相の
パルス列を出力する3分周部と、上記3つの状態
の任意の1状態におけるクロツクパルスの変化を
検出する検出手段と、この検出手段で得られたク
ロツクパルスの変化と前記1状態より1つ前の状
態変化とに対して反転動作する第3のフリツプフ
ロツプとから成る3分周回路。
a 3-frequency divider configured by at least a first and a second flip-flop and outputting at least a two-phase pulse train that repeatedly forms three different states in synchronization with a clock pulse; and a clock pulse in any one of the three states. and a third flip-flop circuit that operates inverted with respect to a change in the clock pulse obtained by the detection means and a change in the state one state before the first state.
JP14009884U 1984-09-14 1984-09-14 Pending JPS6157632U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14009884U JPS6157632U (en) 1984-09-14 1984-09-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14009884U JPS6157632U (en) 1984-09-14 1984-09-14

Publications (1)

Publication Number Publication Date
JPS6157632U true JPS6157632U (en) 1986-04-18

Family

ID=30698457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14009884U Pending JPS6157632U (en) 1984-09-14 1984-09-14

Country Status (1)

Country Link
JP (1) JPS6157632U (en)

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