JPS6399417U - - Google Patents

Info

Publication number
JPS6399417U
JPS6399417U JP19616586U JP19616586U JPS6399417U JP S6399417 U JPS6399417 U JP S6399417U JP 19616586 U JP19616586 U JP 19616586U JP 19616586 U JP19616586 U JP 19616586U JP S6399417 U JPS6399417 U JP S6399417U
Authority
JP
Japan
Prior art keywords
input
flop
exclusive
pulse train
type flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19616586U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19616586U priority Critical patent/JPS6399417U/ja
Publication of JPS6399417U publication Critical patent/JPS6399417U/ja
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の原理を説明する図、第2図は
本考案を用いた一実施例を示す図、第3図は従来
例の回路図である。 1はイクスクルーシブ・オア(E―OR)、2
はフリツプフロツプ(D―FF)。
FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a diagram showing an embodiment using the present invention, and FIG. 3 is a circuit diagram of a conventional example. 1 is exclusive or (E-OR), 2
is a flip-flop (D-FF).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] イクスクルーシブ・オア1の一方の入力にパル
ス列を入力し、イクスクルーシブ・オア1の出力
をD型フリツプフロツプのクロツク入力に接続し
、D型フリツプフロツプ2の出力をD型フリツ
プフロツプ2のD入力およびイクスクルーシブ・
オア1の他の一方の入力に接続し、入力パルス列
の立ち上がりおよび立ち下がりを検出することに
より、入力パルス列の周波数を2倍に変換するこ
とを特徴とした2倍周回路。
A pulse train is input to one input of exclusive OR 1, the output of exclusive OR 1 is connected to the clock input of a D-type flip-flop, and the output of D-type flip-flop 2 is connected to the D input of D-type flip-flop 2 and Exclusive
A frequency doubling circuit characterized in that it is connected to the other input of OR 1 and doubles the frequency of an input pulse train by detecting the rising and falling edges of the input pulse train.
JP19616586U 1986-12-18 1986-12-18 Pending JPS6399417U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19616586U JPS6399417U (en) 1986-12-18 1986-12-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19616586U JPS6399417U (en) 1986-12-18 1986-12-18

Publications (1)

Publication Number Publication Date
JPS6399417U true JPS6399417U (en) 1988-06-28

Family

ID=31154734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19616586U Pending JPS6399417U (en) 1986-12-18 1986-12-18

Country Status (1)

Country Link
JP (1) JPS6399417U (en)

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