JPS61193381U - - Google Patents
Info
- Publication number
- JPS61193381U JPS61193381U JP7802785U JP7802785U JPS61193381U JP S61193381 U JPS61193381 U JP S61193381U JP 7802785 U JP7802785 U JP 7802785U JP 7802785 U JP7802785 U JP 7802785U JP S61193381 U JPS61193381 U JP S61193381U
- Authority
- JP
- Japan
- Prior art keywords
- phase difference
- waveforms
- clock pulses
- counting
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Measuring Phase Differences (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は同上の動作を示す波形図、第３図は本考案の
他の実施例を示すフローチヤート、第４図は従来
例の回路図、第５図は同上の動作を示す波形図で
ある。
ＳＨ１，ＳＨ２…波形整形回路、ＮＯＴ…イン
バータ回路、ＦＦ…ＲＳフリツプフロツプ、ＯＳ
Ｃ…パルス発振器、ＡＮＤ…アンドゲート、ＣＮ
Ｔ…カウンタ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
3 is a flowchart showing another embodiment of the present invention, FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a waveform diagram showing the same operation. SH1, SH2...Waveform shaping circuit, NOT...Inverter circuit, FF...RS flip-flop, OS
C...Pulse oscillator, AND...And gate, CN
T...Counter.
Claims (1)
それぞれ波形整形し、両波形の不一致期間に含ま
れるクロツクパルス数をカウントして位相差を計
測するようにしたデイジタル位相差計において、
一方の波形を反転すると共に、両波形の立上り（
または立下り）間のクロツクパルスをカウントす
ることにより、位相差をデイジタル量で出力する
ようにしたことを特徴とするデイジタル位相差計
。 A digital phase difference meter that measures the phase difference by shaping the voltage and current signals introduced from the power system and counting the number of clock pulses included in the mismatch period between the two waveforms.
While inverting one waveform, the rise of both waveforms (
1. A digital phase difference meter, characterized in that the phase difference is output as a digital quantity by counting clock pulses during periods (or falling edges).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7802785U JPS61193381U (en) | 1985-05-24 | 1985-05-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7802785U JPS61193381U (en) | 1985-05-24 | 1985-05-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61193381U true JPS61193381U (en) | 1986-12-02 |
Family
ID=30621635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7802785U Pending JPS61193381U (en) | 1985-05-24 | 1985-05-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61193381U (en) |
-
1985
- 1985-05-24 JP JP7802785U patent/JPS61193381U/ja active Pending
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