JPS61203367U - - Google Patents
Info
- Publication number
- JPS61203367U JPS61203367U JP8776785U JP8776785U JPS61203367U JP S61203367 U JPS61203367 U JP S61203367U JP 8776785 U JP8776785 U JP 8776785U JP 8776785 U JP8776785 U JP 8776785U JP S61203367 U JPS61203367 U JP S61203367U
- Authority
- JP
- Japan
- Prior art keywords
- phase difference
- current
- waveform
- clock pulses
- counting clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Measuring Phase Differences (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
第１図は本発明の一実施例を示すブロツク回路
図、第２図ａ，ｂは同上の動作を示すフローチヤ
ート、第３図ａ，ｂは同上の波形図、第４図は従
来例のブロツク回路図、第５図ａ，ｂは同上の波
形図である。
ＰＴ……変圧器、ＣＴ……変流器、Ｓ１，Ｓ２
……波形整形回路、ＦＦ……フリツプフロツプ、
ＮＯＴ……インバータ、ＡＮＤ……アンドゲート
、ＣＰＵ……マイクロコンピユータ、ＣＣ……カ
ウンタ。
FIG. 1 is a block circuit diagram showing an embodiment of the present invention, FIGS. 2a and b are flowcharts showing the same operation, FIGS. 3a and b are waveform diagrams of the same, and FIG. 4 is a conventional example. The block circuit diagram and FIGS. 5a and 5b are waveform diagrams of the same. PT...Transformer, CT...Current transformer, S1 , S2
...waveform shaping circuit, FF...flip-flop,
NOT...Inverter, AND...And gate, CPU...Microcomputer, CC...Counter.
Claims (1)
形整形し、これら二つの波形整形出力の一方でセ
ツトされた他方でリセツトされるフリツプフロツ
プの出力パルス幅内でクロツクパルスをカウント
する手段を設けて、電圧と電流の位相差をデイジ
タル値に変換するようにしたデイジタル位相差計
において、別途電圧または電流の１サイクル中の
クロツクパルスをカウントする手段を設けて、上
記両カウント値の比により位相差を演算するよう
にして成るデイジタル位相差計。 A voltage signal and a current signal introduced from the power system are waveform-shaped, and a means is provided for counting clock pulses within the output pulse width of a flip-flop, where one of these two waveform-shaped outputs is set and the other is reset. In a digital phase difference meter that converts the phase difference of current into a digital value, a means for counting clock pulses during one cycle of voltage or current is separately provided, and the phase difference is calculated by the ratio of the two count values. A digital phase difference meter consisting of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8776785U JPS61203367U (en) | 1985-06-10 | 1985-06-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8776785U JPS61203367U (en) | 1985-06-10 | 1985-06-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61203367U true JPS61203367U (en) | 1986-12-20 |
Family
ID=30640288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8776785U Pending JPS61203367U (en) | 1985-06-10 | 1985-06-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61203367U (en) |
-
1985
- 1985-06-10 JP JP8776785U patent/JPS61203367U/ja active Pending