JPS6210680U - - Google Patents

Info

Publication number
JPS6210680U
JPS6210680U JP10156985U JP10156985U JPS6210680U JP S6210680 U JPS6210680 U JP S6210680U JP 10156985 U JP10156985 U JP 10156985U JP 10156985 U JP10156985 U JP 10156985U JP S6210680 U JPS6210680 U JP S6210680U
Authority
JP
Japan
Prior art keywords
circuit
phase clock
pulse width
count
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10156985U
Other languages
Japanese (ja)
Other versions
JPH0318950Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10156985U priority Critical patent/JPH0318950Y2/ja
Publication of JPS6210680U publication Critical patent/JPS6210680U/ja
Application granted granted Critical
Publication of JPH0318950Y2 publication Critical patent/JPH0318950Y2/ja
Expired legal-status Critical Current

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  • Manipulation Of Pulses (AREA)
  • Measuring Phase Differences (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案の実施例における回路ブロツ
ク図、第2図は、第1図の動作波形図、第3図は
、従来のパルス幅測定回路のブロツク図である。 2……クロツク発生回路、5……逆相クロツク
発生回路、6,7……カウンタ、8……加算器。
FIG. 1 is a circuit block diagram of an embodiment of the present invention, FIG. 2 is an operating waveform diagram of FIG. 1, and FIG. 3 is a block diagram of a conventional pulse width measuring circuit. 2...Clock generation circuit, 5...Negative phase clock generation circuit, 6, 7...Counter, 8...Adder.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 正相クロツクおよび逆相クロツクを発生するク
ロツク回路のそれぞれの出力を、正相クロツクカ
ウンタ回路と逆相クロツクカウンタ回路に接続し
、また、前記各カウンタ回路のカウント開始端子
には被測定パルスを入力し、上記カウント回路の
それぞれの出力を加算器にて加算し、パルス幅に
応じたカウント出力を得る回路構成とし、さらに
、上記被測定パルスから生成する上記カウント回
路のクリヤ信号および、加算器の加算開始信号を
発生する回路をも有する回路構成としたことを特
徴とするパルス幅測定回路。
The respective outputs of the clock circuits that generate the positive phase clock and the negative phase clock are connected to the positive phase clock counter circuit and the negative phase clock counter circuit, and the count start terminal of each counter circuit is connected to the pulse to be measured. is input, the outputs of each of the count circuits are added by an adder, and a count output corresponding to the pulse width is obtained. 1. A pulse width measuring circuit characterized in that the circuit has a circuit configuration that also includes a circuit that generates an addition start signal for a pulse width measuring circuit.
JP10156985U 1985-07-03 1985-07-03 Expired JPH0318950Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10156985U JPH0318950Y2 (en) 1985-07-03 1985-07-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10156985U JPH0318950Y2 (en) 1985-07-03 1985-07-03

Publications (2)

Publication Number Publication Date
JPS6210680U true JPS6210680U (en) 1987-01-22
JPH0318950Y2 JPH0318950Y2 (en) 1991-04-22

Family

ID=30972412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10156985U Expired JPH0318950Y2 (en) 1985-07-03 1985-07-03

Country Status (1)

Country Link
JP (1) JPH0318950Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63274863A (en) * 1987-05-01 1988-11-11 Tsuzuki Boseki Kk Method and device for detecting foreign matter in raw cotton

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63274863A (en) * 1987-05-01 1988-11-11 Tsuzuki Boseki Kk Method and device for detecting foreign matter in raw cotton

Also Published As

Publication number Publication date
JPH0318950Y2 (en) 1991-04-22

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