JPS6333218U - - Google Patents
Info
- Publication number
- JPS6333218U JPS6333218U JP12675286U JP12675286U JPS6333218U JP S6333218 U JPS6333218 U JP S6333218U JP 12675286 U JP12675286 U JP 12675286U JP 12675286 U JP12675286 U JP 12675286U JP S6333218 U JPS6333218 U JP S6333218U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- reached
- reset signal
- set time
- measuring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第1図は本考案の第1の実施例におけるリセツ
ト回路の構成図、第2図は本考案の第2の実施例
におけるリセツト回路の構成図、第3図は本考案
の第1の実施例のリセツト回路における各種信号
のタイミングチヤート、第4図は本考案の第2の
実施例のリセツト回路における各種信号のタイミ
ングチヤート、第5図は従来のリセツト回路の説
明図である。
1:電圧検出回路、2:ラツチ、3:カウンタ
、4:発振器、21:リセツトIC,22:リセ
ツトIC出力、23:積分回路出力、24:増幅
回路出力、31:出力(インバータ32の入力電
圧),32,33:インバータ、ON:電源ON
信号、CON:カウンタON信号、CLOCK:
クロツク、TC:設定時間終了信号、RESET
:リセツト信号、C:コンデンサ、R,R1,R
2:抵抗、Di:ダイオード。
Fig. 1 is a block diagram of a reset circuit in a first embodiment of the present invention, Fig. 2 is a block diagram of a reset circuit in a second embodiment of the present invention, and Fig. 3 is a block diagram of a reset circuit in a first embodiment of the present invention. FIG. 4 is a timing chart of various signals in the reset circuit of the second embodiment of the present invention, and FIG. 5 is an explanatory diagram of a conventional reset circuit. 1: Voltage detection circuit, 2: Latch, 3: Counter, 4: Oscillator, 21: Reset IC, 22: Reset IC output, 23: Integrator circuit output, 24: Amplifier circuit output, 31: Output (input voltage of inverter 32) ), 32, 33: Inverter, ON: Power ON
Signal, CON: Counter ON signal, CLOCK:
Clock, TC: Set time end signal, RESET
: Reset signal, C: Capacitor, R, R 1 , R
2 : Resistor, Di: Diode.
Claims (1)
を発生するリセツト回路において、上記電源電圧
が上記電子回路の動作保証電圧に達したことを検
知する手段、および、上記リセツト信号の出力時
間を計測する手段を設け、該検知手段が該動作保
証電圧に達したことを検知すると、該リセツト信
号をON状態とし、該計測手段は、該リセツト信
号の出力時間が予め設定された時間になるまで計
測し、該設定時間に達すると、該リセツト信号を
OFF状態にすることを特徴とするリセツト回路
。 2 上記計測手段は、クロツク信号を計測するこ
とにより、上記設定時間を計測することを特徴と
する実用新案登録請求範囲第1項記載のリセツト
回路。[Claims for Utility Model Registration] 1. In a reset circuit that generates a reset signal according to the power supply voltage of the electronic circuit, means for detecting that the power supply voltage has reached the operation guaranteed voltage of the electronic circuit; Means for measuring the output time of the reset signal is provided, and when the detection means detects that the operation guaranteed voltage is reached, the reset signal is turned on, and the measuring means sets the output time of the reset signal to the preset value. What is claimed is: 1. A reset circuit that measures a set time until a set time is reached, and turns off the reset signal when the set time is reached. 2. The reset circuit according to claim 1, wherein the measuring means measures the set time by measuring a clock signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12675286U JPS6333218U (en) | 1986-08-20 | 1986-08-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12675286U JPS6333218U (en) | 1986-08-20 | 1986-08-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6333218U true JPS6333218U (en) | 1988-03-03 |
Family
ID=31020859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12675286U Pending JPS6333218U (en) | 1986-08-20 | 1986-08-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6333218U (en) |
-
1986
- 1986-08-20 JP JP12675286U patent/JPS6333218U/ja active Pending
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