JPS63161371U - - Google Patents
Info
- Publication number
- JPS63161371U JPS63161371U JP5526087U JP5526087U JPS63161371U JP S63161371 U JPS63161371 U JP S63161371U JP 5526087 U JP5526087 U JP 5526087U JP 5526087 U JP5526087 U JP 5526087U JP S63161371 U JPS63161371 U JP S63161371U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output voltage
- buffer
- voltage
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第1図は本考案の一実施例による抵抗測定装置
の回路を示す図である。第2図は従来の抵抗測定
装置の回路を示す図である。第3図は第2図に示
した積分器の入出力電圧を示すタイミングチヤー
トである。
40……被測定抵抗、42……基準抵抗、44
……電源、46……バツフア、48……除算器、
50……インバータ、52……加算器、54……
乗算器、56……抵抗測定装置。
FIG. 1 is a diagram showing a circuit of a resistance measuring device according to an embodiment of the present invention. FIG. 2 is a diagram showing a circuit of a conventional resistance measuring device. FIG. 3 is a timing chart showing the input and output voltages of the integrator shown in FIG. 40...Resistance to be measured, 42...Reference resistance, 44
...power supply, 46...buffer, 48...divider,
50... Inverter, 52... Adder, 54...
Multiplier, 56... resistance measuring device.
Claims (1)
両端に並列接続された電源と、被測定抵抗の両端
電圧を入力とするバツフアと、バツフアの出力電
圧を入力とするインバータと、電源電圧とインバ
ータの出力電圧とを入力とし、それを加算する加
算器と、バツフアと加算器の出力電圧とを入力と
し、バツフアの出力電圧を加算器の出力電圧で除
算する除算器と、除算器の出力電圧を入力とし、
その入力電圧と基準抵抗値とを乗算して被測定抵
抗値を算出する乗算器とから成ることを特徴とす
る抵抗測定装置。 A reference resistor connected in series to the resistor to be measured, a power supply connected in parallel to both ends of the reference resistor, a buffer that receives the voltage across the resistor to be measured as input, an inverter that receives the output voltage of the buffer as input, and a power supply voltage and inverter. an adder that takes the output voltage of the buffer as an input and adds them; a divider that takes the output voltage of the buffer and the adder as input and divides the output voltage of the buffer by the output voltage of the adder; and an output voltage of the divider. As input,
A resistance measuring device comprising a multiplier that calculates a resistance value to be measured by multiplying the input voltage and a reference resistance value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5526087U JPS63161371U (en) | 1987-04-11 | 1987-04-11 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5526087U JPS63161371U (en) | 1987-04-11 | 1987-04-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63161371U true JPS63161371U (en) | 1988-10-21 |
Family
ID=30882999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5526087U Pending JPS63161371U (en) | 1987-04-11 | 1987-04-11 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63161371U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02194367A (en) * | 1988-09-23 | 1990-07-31 | John Fluke Mfg Co Inc | Electrostatic measuring apparatus and method |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61210965A (en) * | 1985-03-15 | 1986-09-19 | Inoue Denki Seisakusho:Kk | Measuring equipment for low resistance |
-
1987
- 1987-04-11 JP JP5526087U patent/JPS63161371U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61210965A (en) * | 1985-03-15 | 1986-09-19 | Inoue Denki Seisakusho:Kk | Measuring equipment for low resistance |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02194367A (en) * | 1988-09-23 | 1990-07-31 | John Fluke Mfg Co Inc | Electrostatic measuring apparatus and method |
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