JPH0246435U - - Google Patents
Info
- Publication number
- JPH0246435U JPH0246435U JP12481288U JP12481288U JPH0246435U JP H0246435 U JPH0246435 U JP H0246435U JP 12481288 U JP12481288 U JP 12481288U JP 12481288 U JP12481288 U JP 12481288U JP H0246435 U JPH0246435 U JP H0246435U
- Authority
- JP
- Japan
- Prior art keywords
- type flip
- flop
- input
- clock
- flops
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Manipulation Of Pulses (AREA)
Description
第1図は本考案の第1の実施例のクロツク・ジ
エネレータを示す回路ブロツク図、第2図は第1
図の動作波形を示す波形図、第3図は本考案の第
2の実施例のクロツク・ジエネレータを示す回路
ブロツク図、第4図は第3図の動作波形を示す波
形図、第5図は従来のクロツク・ジエネレータを
示す回路ブロツク図、第6図は第5図の動作波形
を示す波形図である。
1,2…D型フリツプフロツプ、3…論理ゲー
ト、4,5…ORゲート、11…クロツク信号、
12…第1の出力信号、13…第2の出力信号、
14…第2の出力の反転出力信号、15…合成出
力信号、16…リセツト信号。
FIG. 1 is a circuit block diagram showing a clock generator according to a first embodiment of the present invention, and FIG.
3 is a circuit block diagram showing the clock generator of the second embodiment of the present invention. FIG. 4 is a waveform diagram showing the operating waveforms of FIG. 3. FIG. 5 is a waveform diagram showing the operating waveforms of FIG. FIG. 6 is a circuit block diagram showing a conventional clock generator, and FIG. 6 is a waveform diagram showing the operating waveforms of FIG. 1, 2... D-type flip-flop, 3... logic gate, 4, 5... OR gate, 11... clock signal,
12...first output signal, 13...second output signal,
14...Inverted output signal of the second output, 15... Combined output signal, 16... Reset signal.
Claims (1)
とも1つの論理ゲートとを含み、前記第1のD型
フリツプフロツプの非反転出力は、前記第2のD
型フリツプフロツプのD入力まで導入されるとと
もに前記論理ゲートの入力に接続され、前記第2
のD型フリツプフロツプの反転出力は、前記第1
のD型フリツプフロツプのD入力にまで導入され
、非反転出力は前記論理ゲートの他の入力に接続
され、クロツク信号は前記第1及び第2のD型フ
リツプフロツプのクロツク入力に接続され、前記
論理ゲートの出力を多相クロツク信号として取り
出すことを特徴とするクロツク・ジエネレータ。 The flip-flop includes first and second D-type flip-flops and at least one logic gate, and the non-inverting output of the first D-type flip-flop is connected to the second D-type flip-flop.
The D input of the type flip-flop is connected to the input of the logic gate, and the second
The inverted output of the D-type flip-flop is
The non-inverting output is connected to the other input of the logic gate, the clock signal is connected to the clock input of the first and second D-type flip-flops, and the clock signal is connected to the clock input of the first and second D-type flip-flops. A clock generator characterized in that the output of the clock generator is extracted as a multiphase clock signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12481288U JPH0246435U (en) | 1988-09-22 | 1988-09-22 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12481288U JPH0246435U (en) | 1988-09-22 | 1988-09-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0246435U true JPH0246435U (en) | 1990-03-29 |
Family
ID=31374868
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12481288U Pending JPH0246435U (en) | 1988-09-22 | 1988-09-22 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0246435U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4890451A (en) * | 1972-02-29 | 1973-11-26 |
-
1988
- 1988-09-22 JP JP12481288U patent/JPH0246435U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4890451A (en) * | 1972-02-29 | 1973-11-26 |
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