JPH0223725U

JPH0223725U -

Info

Publication number: JPH0223725U
Application number: JP10028288U
Authority: JP
Priority date: 1988-07-27
Filing date: 1988-07-27
Publication date: 1990-02-16

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示す回路ブロツク
図、第２図はその各部の動作波形を示す波形図、
第３図は本考案の他の実施例を示す回路ブロツク
図、第４図はその各部の動作波形を示す波形図、
第５図は従来例の構成を示す回路ブロツク図であ
る。１……データ入力端子、２……遅延素子、３…
…インバータ、４，５……フリツプ・フロツプ、
６……ＮＯＲ素子、７……データ出力端子、８…
…データ入力端子、９……遅延素子、１０……イ
ンバータ、１１，１２……フリツプ・フロツプ、
１３……インバータ、１４……ＮＡＮＤ素子、１
５……データ出力端子、１６……＋５Ｖ入力端子
、１７……抵抗、１８……コンデンサ、１９……
クロツク入力端子、２０……マルチバイブレータ
、２１……検出信号出力端子。 FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram showing operating waveforms of each part.
FIG. 3 is a circuit block diagram showing another embodiment of the present invention, and FIG. 4 is a waveform diagram showing operating waveforms of each part.
FIG. 5 is a circuit block diagram showing the configuration of a conventional example. 1...Data input terminal, 2...Delay element, 3...
...Inverter, 4,5...Flip-flop,
6...NOR element, 7...data output terminal, 8...
...Data input terminal, 9...Delay element, 10...Inverter, 11, 12...Flip-flop,
13...Inverter, 14...NAND element, 1
5...Data output terminal, 16...+5V input terminal, 17...Resistor, 18...Capacitor, 19...
Clock input terminal, 20...multivibrator, 21...detection signal output terminal.

Claims

[Scope of utility model registration request]

first and second flip-flops having a signal input, a clock input, and normal and inverted outputs; and data inputs connected to the signal inputs of the first and second flip-flops. a delay element connected between the data input terminal and the clock input terminal of the first flip-flop; and a delay element connected between the clock input terminal of the first flip-flop and the second flip-flop. an inverter connected between the clock input terminal of the flip-flop . 1. A clock break detection circuit comprising: a circuit for obtaining a logical product of outputs of a flop.