JPS61109232U - - Google Patents
Info
- Publication number
- JPS61109232U JPS61109232U JP19393484U JP19393484U JPS61109232U JP S61109232 U JPS61109232 U JP S61109232U JP 19393484 U JP19393484 U JP 19393484U JP 19393484 U JP19393484 U JP 19393484U JP S61109232 U JPS61109232 U JP S61109232U
- Authority
- JP
- Japan
- Prior art keywords
- pulse generating
- inverter
- signal line
- generating circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は第１図に示された回路の動作を示す波形図、第
３図は従来例を示す回路図である。
８……入力パツド、９……信号線、１０……保
護抵抗、１１……保護ダイオード、１２……ＭＯ
ＳＦＥＴ、１３……コンデンサ、１４……第１の
インバータ、１５……第２のインバータ、１６…
…第１のパルス発生回路、１９……第２のパルス
発生回路、２２……フリツプフロツプ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing a conventional example. 8...Input pad, 9...Signal line, 10...Protection resistor, 11...Protection diode, 12...MO
SFET, 13... Capacitor, 14... First inverter, 15... Second inverter, 16...
...first pulse generating circuit, 19...second pulse generating circuit, 22...flip-flop.
Claims (1)
ートが共通に接続されたスレツシヨルド電圧の異
なる第１のインバータ及び第２のインバータと、
該第１及び第２のインバータの出力を入力とする
第１のパルス発生回路及び第２のパルス発生回路
と、該第１及び第２のパルス発生回路のパルスに
よつてセツト及びリセツトされるフリツプフロツ
プとを備えて成る波形整形回路。 a signal line to which a signal is applied, a first inverter and a second inverter having different threshold voltages and whose input gates are commonly connected to the signal line;
a first pulse generating circuit and a second pulse generating circuit that receive the outputs of the first and second inverters; and a flip-flop that is set and reset by the pulses of the first and second pulse generating circuits. A waveform shaping circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19393484U JPS61109232U (en) | 1984-12-20 | 1984-12-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19393484U JPS61109232U (en) | 1984-12-20 | 1984-12-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61109232U true JPS61109232U (en) | 1986-07-10 |
Family
ID=30751367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19393484U Pending JPS61109232U (en) | 1984-12-20 | 1984-12-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61109232U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009060345A (en) * | 2007-08-31 | 2009-03-19 | Seiko Instruments Inc | Voltage detection circuit and oscillator using the same |
-
1984
- 1984-12-20 JP JP19393484U patent/JPS61109232U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009060345A (en) * | 2007-08-31 | 2009-03-19 | Seiko Instruments Inc | Voltage detection circuit and oscillator using the same |
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