JPS61195127U

JPS61195127U -

Info

Publication number: JPS61195127U
Application number: JP5900985U
Authority: JP
Priority date: 1985-04-19
Filing date: 1985-04-19
Publication date: 1986-12-05

Description

[Brief explanation of drawings]

第１図は本考案の論理回路の１実施例の回路構
成図、第２図、第３図は１つのＮＯＲゲートの一
方の入力端子を異なる所定、電位に固定してなる
ものの入出力特性図、第４図は第１図の実施例か
らインバータを外したものの入出力特性図、第５
図は本考案の他の実施例の回路構成図、第６図は
第２実施例の入出力特性図である。３……第１の論理ゲート、４……第２の論理ゲ
ート、５，５′……第３の論理ゲート。 Figure 1 is a circuit configuration diagram of one embodiment of the logic circuit of the present invention, and Figures 2 and 3 are input/output characteristic diagrams of one NOR gate with one input terminal fixed at different predetermined potentials. , FIG. 4 is an input/output characteristic diagram of the embodiment shown in FIG. 1 with the inverter removed, and FIG.
The figure is a circuit configuration diagram of another embodiment of the present invention, and FIG. 6 is an input/output characteristic diagram of the second embodiment. 3...First logic gate, 4...Second logic gate, 5, 5'...Third logic gate.

Claims

[Claims for Utility Model Registration] (1) A first logic gate in which a certain reference voltage is applied to one input terminal and the other input terminal and the output terminal are connected, and an input signal is applied to one input terminal. a second logic gate in which the other input terminal and the output terminal of the first logic gate are connected; and a third logic gate into which a signal from the output terminal of the second logic gate is input; A logic circuit that determines and outputs a high level or a low level of the input signal using the reference voltage as a boundary to an output terminal of a third logic gate. (2) The third logic gate has a first input terminal into which the signal from the output terminal of the second logic gate is input, and a second input terminal into which the reference voltage is input. Utility model registration. Claim No. (1)
Logic circuit described in section.