JPS6170259U

JPS6170259U -

Info

Publication number: JPS6170259U
Application number: JP15921985U
Authority: JP
Priority date: 1985-10-16
Filing date: 1985-10-16
Publication date: 1986-05-14

Description

[Brief explanation of drawings]

第１図は従来の２値化回路を示す図、第２図は
この考案の一実施例を示す回路図、第３図は第２
図の選択器の一例を示す回路図、第４図は各部の
信号波形図である。図中、３００，３０１は比較器、３０２は選択
器、４０１はフリツプフロツプ素子、４０２はイ
ンバータ、４０３，４０４はアンドゲート素子、
４０５はオアゲート素子である。なお、図中、同
一符号は、同一又は相当部分を示す。 Fig. 1 is a diagram showing a conventional binarization circuit, Fig. 2 is a circuit diagram showing an embodiment of this invention, and Fig. 3 is a diagram showing a conventional binarization circuit.
FIG. 4 is a circuit diagram showing an example of the selector shown in the figure, and FIG. 4 is a signal waveform diagram of each part. In the figure, 300 and 301 are comparators, 302 is a selector, 401 is a flip-flop element, 402 is an inverter, 403 and 404 are AND gate elements,
405 is an OR gate element. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

A first comparator that compares the image signal with a threshold of a predetermined level, a second comparator that compares the image signal with a threshold of a level higher than the threshold, and each output of both comparators is selected. a flip-flop element, the selector having the output of the second comparator supplied to the set input terminal and the output of the first comparator supplied to the reset input terminal via an inverter; an AND gate element supplied with the set output of the element and the output of the second comparator; an AND gate element supplied with the reset output of the flip-flop element and the output of the first comparator; and outputs of both AND gate elements. 1. A binarization circuit comprising: an OR element supplied with .