JPS61334U - Tri-state gate element chip - Google Patents

Tri-state gate element chip

Info

Publication number
JPS61334U
JPS61334U JP8322284U JP8322284U JPS61334U JP S61334 U JPS61334 U JP S61334U JP 8322284 U JP8322284 U JP 8322284U JP 8322284 U JP8322284 U JP 8322284U JP S61334 U JPS61334 U JP S61334U
Authority
JP
Japan
Prior art keywords
tri
gate element
state gate
element chip
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8322284U
Other languages
Japanese (ja)
Inventor
敏彦 高橋
Original Assignee
株式会社明電舎
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社明電舎 filed Critical 株式会社明電舎
Priority to JP8322284U priority Critical patent/JPS61334U/en
Publication of JPS61334U publication Critical patent/JPS61334U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例を示す構成図、第2図は、第1
図に示すトライステートゲート素子チツプの利用例を示
す回路図、第3図は本考案の他の実施例及びその利用例
を同時に示す回路図、第4図及び第5図はトライステー
トゲート素子を用いた従来の回路構成を示す回路図であ
る。 1・・・トライステートゲート素子、2・・・信号ライ
ン、3・・・レシーバ、5・・・トライステートゲート
素子、7.10・・・トライステートゲート素子チッ−
ブ、R0−0プルアップ抵抗。
FIG. 1 is a configuration diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing another embodiment of the present invention and its usage example; FIGS. 4 and 5 are circuit diagrams showing an example of how the tri-state gate element chip shown in FIG. FIG. 2 is a circuit diagram showing a conventional circuit configuration used. DESCRIPTION OF SYMBOLS 1... Tri-state gate element, 2... Signal line, 3... Receiver, 5... Tri-state gate element, 7.10... Tri-state gate element chip.
B, R0-0 pull-up resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] トライステートゲート素子と、この素子の出力側に接続
されたプルアップ抵抗とを一体化して成ることを特徴と
するトライステートゲート素子チップ。
A tri-state gate element chip characterized by integrating a tri-state gate element and a pull-up resistor connected to the output side of this element.
JP8322284U 1984-06-05 1984-06-05 Tri-state gate element chip Pending JPS61334U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8322284U JPS61334U (en) 1984-06-05 1984-06-05 Tri-state gate element chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8322284U JPS61334U (en) 1984-06-05 1984-06-05 Tri-state gate element chip

Publications (1)

Publication Number Publication Date
JPS61334U true JPS61334U (en) 1986-01-06

Family

ID=30631650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8322284U Pending JPS61334U (en) 1984-06-05 1984-06-05 Tri-state gate element chip

Country Status (1)

Country Link
JP (1) JPS61334U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6380651U (en) * 1986-11-12 1988-05-27

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6380651U (en) * 1986-11-12 1988-05-27

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