JPS5868723U - Frequency characteristic circuit - Google Patents

Frequency characteristic circuit

Info

Publication number
JPS5868723U
JPS5868723U JP16259681U JP16259681U JPS5868723U JP S5868723 U JPS5868723 U JP S5868723U JP 16259681 U JP16259681 U JP 16259681U JP 16259681 U JP16259681 U JP 16259681U JP S5868723 U JPS5868723 U JP S5868723U
Authority
JP
Japan
Prior art keywords
frequency characteristic
characteristic circuit
frequency
circuit
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16259681U
Other languages
Japanese (ja)
Inventor
茂 大川
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP16259681U priority Critical patent/JPS5868723U/en
Publication of JPS5868723U publication Critical patent/JPS5868723U/en
Pending legal-status Critical Current

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  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1実施例の回路の回路図、第2図は
その第1実施例の回路の周波数特性図、第3図は第2実
施例の回路の回路図、第4図はその第2実施例の回路の
周波数特性図、第5図は第3実施例の回路の回路図、第
6図は第4実施例の回路の回路図である。2
Fig. 1 is a circuit diagram of the circuit of the first embodiment of the present invention, Fig. 2 is a frequency characteristic diagram of the circuit of the first embodiment, Fig. 3 is a circuit diagram of the circuit of the second embodiment, and Fig. 4 is a frequency characteristic diagram of the circuit of the second embodiment, FIG. 5 is a circuit diagram of the circuit of the third embodiment, and FIG. 6 is a circuit diagram of the circuit of the fourth embodiment. 2

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号の周波数によりインピーダンスが変化するイン
ピーダンス素子に対して、並列に非直線性素子を接続し
て成ることを特゛徴とする周波数特性回路。
A frequency characteristic circuit characterized in that a nonlinear element is connected in parallel to an impedance element whose impedance changes depending on the frequency of an input signal.
JP16259681U 1981-11-02 1981-11-02 Frequency characteristic circuit Pending JPS5868723U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16259681U JPS5868723U (en) 1981-11-02 1981-11-02 Frequency characteristic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16259681U JPS5868723U (en) 1981-11-02 1981-11-02 Frequency characteristic circuit

Publications (1)

Publication Number Publication Date
JPS5868723U true JPS5868723U (en) 1983-05-10

Family

ID=29954905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16259681U Pending JPS5868723U (en) 1981-11-02 1981-11-02 Frequency characteristic circuit

Country Status (1)

Country Link
JP (1) JPS5868723U (en)

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