JPS599642U - timer circuit - Google Patents

timer circuit

Info

Publication number
JPS599642U
JPS599642U JP10420682U JP10420682U JPS599642U JP S599642 U JPS599642 U JP S599642U JP 10420682 U JP10420682 U JP 10420682U JP 10420682 U JP10420682 U JP 10420682U JP S599642 U JPS599642 U JP S599642U
Authority
JP
Japan
Prior art keywords
timer circuit
circuit
gate circuit
input terminal
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10420682U
Other languages
Japanese (ja)
Inventor
佐藤 吉正
稲田 雅憲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10420682U priority Critical patent/JPS599642U/en
Publication of JPS599642U publication Critical patent/JPS599642U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のタイマ回路を示す図である。第2図は第
1図の各部の波形図である。第3図は、この考案の一実
施例を示す図である。第4図は第3図の各部の波形図で
ある。 図において、1.10はスイッチ、2,4゜11.13
は抵抗、3.12はコンデンサ、22はORゲートを示
す。
FIG. 1 is a diagram showing a conventional timer circuit. FIG. 2 is a waveform diagram of each part of FIG. 1. FIG. 3 is a diagram showing an embodiment of this invention. FIG. 4 is a waveform diagram of each part of FIG. 3. In the figure, 1.10 is a switch, 2,4°11.13
is a resistor, 3.12 is a capacitor, and 22 is an OR gate.

Claims (1)

【実用新案登録請求の範囲】 複数の入力端子を有するゲート回路、 前記ゲート回路の各入力端子ごとに接続されるコンデン
サと抵抗とを含む時定数回路、および前記ゲート回路の
各入力端子に指令信号を与える手段備えた、タイマ回路
[Claims for Utility Model Registration] A gate circuit having a plurality of input terminals, a time constant circuit including a capacitor and a resistor connected to each input terminal of the gate circuit, and a command signal to each input terminal of the gate circuit. A timer circuit with a means to give
JP10420682U 1982-07-07 1982-07-07 timer circuit Pending JPS599642U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10420682U JPS599642U (en) 1982-07-07 1982-07-07 timer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10420682U JPS599642U (en) 1982-07-07 1982-07-07 timer circuit

Publications (1)

Publication Number Publication Date
JPS599642U true JPS599642U (en) 1984-01-21

Family

ID=30244779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10420682U Pending JPS599642U (en) 1982-07-07 1982-07-07 timer circuit

Country Status (1)

Country Link
JP (1) JPS599642U (en)

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