JPS59113770U - Voltage judgment circuit - Google Patents

Voltage judgment circuit

Info

Publication number
JPS59113770U
JPS59113770U JP734083U JP734083U JPS59113770U JP S59113770 U JPS59113770 U JP S59113770U JP 734083 U JP734083 U JP 734083U JP 734083 U JP734083 U JP 734083U JP S59113770 U JPS59113770 U JP S59113770U
Authority
JP
Japan
Prior art keywords
integrated circuits
judgment circuit
digital integrated
voltage judgment
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP734083U
Other languages
Japanese (ja)
Inventor
明良 阿留多伎
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP734083U priority Critical patent/JPS59113770U/en
Publication of JPS59113770U publication Critical patent/JPS59113770U/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電圧判定回路の一例を示す回路図、第2
図は本考案の一実施例を示す回路図、第3図は上記実施
例の人、出力信号を示す図である。 図において、8・・・電圧測定端子、9・・−CMOS
バッファ回路、10・・−TTLバッファ回路。
Figure 1 is a circuit diagram showing an example of a conventional voltage determination circuit;
The figure is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing output signals of the embodiment. In the figure, 8...voltage measurement terminal, 9...-CMOS
Buffer circuit, 10...-TTL buffer circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力しきい値電圧の異なる複数のデジタル集積回路を備
えて、該複数のデジタル集積回路の入力端子を並列に接
続し、前記複数のデジタル集積回路の出力状態の組合せ
によって入力電圧値を判定することを特徴とする電圧判
定回路。
A plurality of digital integrated circuits having different input threshold voltages are provided, input terminals of the plurality of digital integrated circuits are connected in parallel, and an input voltage value is determined based on a combination of output states of the plurality of digital integrated circuits. A voltage determination circuit featuring:
JP734083U 1983-01-24 1983-01-24 Voltage judgment circuit Pending JPS59113770U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP734083U JPS59113770U (en) 1983-01-24 1983-01-24 Voltage judgment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP734083U JPS59113770U (en) 1983-01-24 1983-01-24 Voltage judgment circuit

Publications (1)

Publication Number Publication Date
JPS59113770U true JPS59113770U (en) 1984-08-01

Family

ID=30138875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP734083U Pending JPS59113770U (en) 1983-01-24 1983-01-24 Voltage judgment circuit

Country Status (1)

Country Link
JP (1) JPS59113770U (en)

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