JPS59106234U

JPS59106234U - Delay circuit in TTL circuit

Info

Publication number: JPS59106234U
Application number: JP1982201234U
Authority: JP
Inventors: 守安藤; 高野　光祥
Original assignee: アンリツ株式会社
Priority date: 1982-12-30
Filing date: 1982-12-30
Publication date: 1984-07-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のＴＴＬ回路における遅延回路の構成例、
第２図は第１図の動作説明図、第３図は従来のＴＴＬ回
路における遅延回路の他の構成例、第４図は第３図の動
作説明図、第５図、第６図は本考案に係るＴＴＬ回路に
おける遅延回路の一実施例構成、第７図はＬレベルにお
けるインピーダンス説明図、第８図はＬレベルにおける
等価回路、第９図はＨレベルにおけるインピーダンス説
明図、第１０図は動作波形説明図、第１１図はアンド回
路の入力段における等価回路、第１２図は入力と出力と
が対応した同一の論理レベルを有する回路構成例を示し
ている。図中、１はアンド回路、２．３は入力端子、４は出力端
子、５は抵抗、６はコンデンサ、７・は積分回路、８は
入力端、９は出力端、１０はバッファ回路、１１は抵抗
、１２はナンド回路、１３はインバータ回路を表わして
いる。Figure 1 shows an example of the configuration of a delay circuit in a conventional TTL circuit.
Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is another configuration example of a delay circuit in a conventional TTL circuit, Fig. 4 is an explanatory diagram of the operation of Fig. 3, and Figs. An embodiment of the configuration of the delay circuit in the TTL circuit according to the invention, FIG. 7 is an explanatory diagram of impedance at L level, FIG. 8 is an equivalent circuit at L level, FIG. 9 is an explanatory diagram of impedance at H level, and FIG. 10 is an explanatory diagram of impedance at L level. An explanatory diagram of operating waveforms, FIG. 11 shows an equivalent circuit at the input stage of an AND circuit, and FIG. 12 shows an example of a circuit configuration in which the input and output correspond to each other and have the same logic level. In the figure, 1 is an AND circuit, 2.3 is an input terminal, 4 is an output terminal, 5 is a resistor, 6 is a capacitor, 7 is an integrating circuit, 8 is an input terminal, 9 is an output terminal, 10 is a buffer circuit, 11 12 represents a resistor, 12 represents a NAND circuit, and 13 represents an inverter circuit.

Claims

[Scope of utility model registration request]

(1) A TTL circuit whose input and output correspond to each other at the same logic level; an integrating circuit connected between an input terminal and an input terminal of the TTL circuit; and the TTL circuit to which the integrating circuit is connected. A delay circuit in a TTL circuit, comprising a resistor connected between an input terminal of the circuit and an output terminal of the TTL circuit.

(2) Utility model registration claim No. 1, characterized in that the TTL circuit whose inputs and outputs have the same logic level and corresponds to each other is an AND circuit having a plurality of input terminals.
) Delay circuit in the TTL circuit described in item 1.

(3) A delay circuit in a TTL circuit according to claim (1), wherein the TTL circuit whose input and output correspond to each other at the same logic level is a buffer circuit.