JPS60158332U - reset circuit - Google Patents
reset circuitInfo
- Publication number
- JPS60158332U JPS60158332U JP4435484U JP4435484U JPS60158332U JP S60158332 U JPS60158332 U JP S60158332U JP 4435484 U JP4435484 U JP 4435484U JP 4435484 U JP4435484 U JP 4435484U JP S60158332 U JPS60158332 U JP S60158332U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- delay means
- reset circuit
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案回路の一実施例の回路図、第２図は第１
図の回路各部の信号波形図である。
１・・・集積回路、２．４．８． １１・・・端子、３
・・・フリップフロップ、５，６，７．９・・・インバ
ータ、１０・・・ナンド回路。Figure 1 is a circuit diagram of one embodiment of the circuit of the present invention, and Figure 2 is a circuit diagram of an embodiment of the circuit of the present invention.
FIG. 3 is a signal waveform diagram of each part of the circuit shown in the figure. 1... integrated circuit, 2.4.8. 11...Terminal, 3
...Flip-flop, 5,6,7.9...Inverter, 10...NAND circuit.
Claims (1)
つ外部よりの信号が入来する端子に接続され、該端子よ
り供給される信号を遅延させる遅延手段と、該遅延手段
よりの信号でセットされ該内蔵回路の作動による信号で
リセットされるフリップ７リツプと、該遅延手段よりの
信号と該フリップフロップの出力信号とよりリセット信
号を生成して該内蔵回路に供給するゲート回路とよりな
るリセット回路。A set consisting of a delay means that outputs a signal from the operation of the built-in circuit of an integrated circuit to the outside and is connected to a terminal through which a signal from the outside is input, and delays the signal supplied from the terminal, and a signal from the delay means. and a gate circuit that generates a reset signal from the signal from the delay means and the output signal of the flip-flop and supplies it to the built-in circuit. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4435484U JPS60158332U (en) | 1984-03-28 | 1984-03-28 | reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4435484U JPS60158332U (en) | 1984-03-28 | 1984-03-28 | reset circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60158332U true JPS60158332U (en) | 1985-10-22 |
| JPH0230929Y2 JPH0230929Y2 (en) | 1990-08-21 |
Family
ID=30556846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4435484U Granted JPS60158332U (en) | 1984-03-28 | 1984-03-28 | reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60158332U (en) |
-
1984
- 1984-03-28 JP JP4435484U patent/JPS60158332U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0230929Y2 (en) | 1990-08-21 |
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