JPS6020098U

JPS6020098U - Output circuit

Info

Publication number: JPS6020098U
Application number: JP10970283U
Authority: JP
Inventors: 池邊　正純
Original assignee: 日本電気株式会社
Priority date: 1983-07-15
Filing date: 1983-07-15
Publication date: 1985-02-12

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の出力回路図、第２図は本考案の出力回路
図、第３図は本考案の一実施例の集積回路パターンの概
略図である。１・・・・・・出力論理回路ブロック、２・・・・・・
出力トラ１　ンジスタブロック、３・・・・・・遅延回
路ブロック、４・・・・・・１．　２．　３の間の可変
接続部、５．　６．　７゜８・・・・・・４の接続設定
用コンタクト、９・・・・・・出力論理回路よりの出力
配線、１０・・・・・・出力”トランジスタへの入力配
線、１１・・・・・・出力トランジスタのゲート部、１
２・・・・・・遅延の無視できる配線、１３・・・・・
・遅延のあるもしくは遅延回路を含んだ配線。FIG. 1 is a conventional output circuit diagram, FIG. 2 is an output circuit diagram of the present invention, and FIG. 3 is a schematic diagram of an integrated circuit pattern of an embodiment of the present invention. 1... Output logic circuit block, 2...
Output transistor 1 transistor block, 3...Delay circuit block, 4...1. 2. a variable connection between 3 and 5. 6. 7゜8...4 connection setting contacts, 9...Output wiring from the output logic circuit, 10...Input wiring to the output transistor, 11...・・・Gate part of output transistor, 1
2... Wiring with negligible delay, 13...
・Wiring that has a delay or includes a delay circuit.

Claims

[Scope of utility model registration request]

A feature is that it is possible to set by code mask whether the input of the output transistor and the output of the output logic circuit in the previous stage are connected by wiring with negligible delay, or by wiring with delay or including a delay circuit. output circuit.