JPS60111126U - Delay circuit with reset - Google Patents

Delay circuit with reset

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Publication number
JPS60111126U
JPS60111126U JP1984184265U JP18426584U JPS60111126U JP S60111126 U JPS60111126 U JP S60111126U JP 1984184265 U JP1984184265 U JP 1984184265U JP 18426584 U JP18426584 U JP 18426584U JP S60111126 U JPS60111126 U JP S60111126U
Authority
JP
Japan
Prior art keywords
delay circuit
reset
cascade
abstract
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984184265U
Other languages
Japanese (ja)
Inventor
和雄 村野
俊隆 津田
典生 村上
一雄 山口
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1984184265U priority Critical patent/JPS60111126U/en
Publication of JPS60111126U publication Critical patent/JPS60111126U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のリセット付遅延回路、第２図は第１図の
動作説明図、第３図は本考案の実施例のリセット付遅延
回路、第４図は第３図の動作説明図である。 ＩＮは入力端子、ＯＵＴは出力端子、０１〜Ｇ５はゲー
ト回路、ｔ１〜ｔ５はゲート回路の遅延時間である。FIG. 1 is a conventional delay circuit with reset, FIG. 2 is an explanatory diagram of the operation of FIG. 1, FIG. 3 is an explanatory diagram of the delay circuit with reset of the embodiment of the present invention, and FIG. be. IN is an input terminal, OUT is an output terminal, 01 to G5 are gate circuits, and t1 to t5 are delay times of the gate circuits.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のゲート回路を縦続接続した遅延回路に於いて、縦
続接続の途中の任意数の段及び最終段に、入力信号と遅
延信号とのアンド条件の出力を得るゲート回路をそれぞ
れ設けたことを特徴とするリセット付遅延回路。A delay circuit in which a plurality of gate circuits are connected in cascade is characterized in that a gate circuit is provided at an arbitrary number of stages in the middle of the cascade connection and at the final stage to obtain an output of an AND condition between an input signal and a delayed signal. Delay circuit with reset.
JP1984184265U 1984-12-06 1984-12-06 Delay circuit with reset Pending JPS60111126U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984184265U JPS60111126U (en) 1984-12-06 1984-12-06 Delay circuit with reset

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984184265U JPS60111126U (en) 1984-12-06 1984-12-06 Delay circuit with reset

Publications (1)

Publication Number Publication Date
JPS60111126U true JPS60111126U (en) 1985-07-27

Family

ID=30741750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984184265U Pending JPS60111126U (en) 1984-12-06 1984-12-06 Delay circuit with reset

Country Status (1)

Country Link
JP (1) JPS60111126U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63226111A (en) * 1986-10-01 1988-09-20 Toshiba Corp Semiconductor integrated circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN=1968 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63226111A (en) * 1986-10-01 1988-09-20 Toshiba Corp Semiconductor integrated circuit

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