JPS60163837U - Synchronous up-down counter circuit - Google Patents
Synchronous up-down counter circuitInfo
- Publication number
- JPS60163837U JPS60163837U JP2580185U JP2580185U JPS60163837U JP S60163837 U JPS60163837 U JP S60163837U JP 2580185 U JP2580185 U JP 2580185U JP 2580185 U JP2580185 U JP 2580185U JP S60163837 U JPS60163837 U JP S60163837U
- Authority
- JP
- Japan
- Prior art keywords
- frequency dividing
- circuit
- synchronous
- down counter
- counter circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronizing For Television (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の同期式アップダウンカウンタの一例を示
す回路図、第2図、第3図は第1図及び第4図に示す回
路のタイミング図、第4図はこの考案による同期式アッ
プダウンカウンタ回路の−゛実施例を示す回路図である
。
図中、1〜4は分周回路、11.12はカウント入力端
子、21〜24は分周回路の入力、31.41,32,
42,33,43は分周回路の出力、51,54,52
,55,53,56はアンドゲート回路、61〜64は
オア回路である。
なお、図中、同一符号は同一、または相当部分を示す。Figure 1 is a circuit diagram showing an example of a conventional synchronous up/down counter, Figures 2 and 3 are timing diagrams of the circuits shown in Figures 1 and 4, and Figure 4 is a synchronous up/down counter according to this invention. FIG. 2 is a circuit diagram showing an embodiment of a down counter circuit. In the figure, 1 to 4 are frequency divider circuits, 11.12 is a count input terminal, 21 to 24 are inputs of the frequency divider circuit, 31.41, 32,
42, 33, 43 are the outputs of the frequency dividing circuit, 51, 54, 52
, 55, 53, and 56 are AND gate circuits, and 61 to 64 are OR circuits. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
続し、上記分周回路の上記アンドゲート回路に、前段分
周回路の出力左、前段性周回に接続された上記アンドゲ
ート回路の出力と、基準パルスとを入力させる′ように
構成して成る同期式アップダウンカウンタ回路。A plurality of frequency dividing circuits are connected in multiple stages through AND gate circuits, and the output left of the preceding frequency dividing circuit is connected to the AND gate circuit of the frequency dividing circuit, and the output of the AND gate circuit connected to the preceding stage frequency dividing circuit is connected to the AND gate circuit of the frequency dividing circuit. , and a reference pulse.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2580185U JPS60163837U (en) | 1985-02-25 | 1985-02-25 | Synchronous up-down counter circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2580185U JPS60163837U (en) | 1985-02-25 | 1985-02-25 | Synchronous up-down counter circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60163837U true JPS60163837U (en) | 1985-10-31 |
JPS6117634Y2 JPS6117634Y2 (en) | 1986-05-29 |
Family
ID=30521209
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2580185U Granted JPS60163837U (en) | 1985-02-25 | 1985-02-25 | Synchronous up-down counter circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60163837U (en) |
-
1985
- 1985-02-25 JP JP2580185U patent/JPS60163837U/en active Granted
Non-Patent Citations (1)
Title |
---|
ELECTRONIC DESIGN 4 * |
Also Published As
Publication number | Publication date |
---|---|
JPS6117634Y2 (en) | 1986-05-29 |
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