JPS6059186U - 1 second timer - Google Patents

1 second timer

Info

Publication number
JPS6059186U
JPS6059186U JP15034783U JP15034783U JPS6059186U JP S6059186 U JPS6059186 U JP S6059186U JP 15034783 U JP15034783 U JP 15034783U JP 15034783 U JP15034783 U JP 15034783U JP S6059186 U JPS6059186 U JP S6059186U
Authority
JP
Japan
Prior art keywords
flip
flop
gate
input terminal
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15034783U
Other languages
Japanese (ja)
Inventor
祥樹 早田
宮中 元士
藤堂 賢司
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP15034783U priority Critical patent/JPS6059186U/en
Publication of JPS6059186U publication Critical patent/JPS6059186U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の1秒タイマの回路図、第2図は第1図
の各部の波形図である。 1〜6・・・フリップフロップ、A・・・クロックパル
  1ス入力端子、H・・・出力端子。
FIG. 1 is a circuit diagram of a one-second timer of the present invention, and FIG. 2 is a waveform diagram of each part of FIG. 1. 1 to 6...Flip-flop, A...Clock pulse 1 input terminal, H...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 分周用のフリップフロップを6箇直列に設け、4段目、
5段目、6段目の各フリップフロップの出力を入力とす
る第1のANDゲートを設け、第1のNANDゲートの
出力と2段目のフリップフロップの出力とを入力とする
第2のANDゲートを設け、第2のANDゲートの出力
をリセット入力端子に、2段目のフリップフロップの出
力をセット入力端子に接続したR−Sフリップフロップ
−を設け、R−Sフリップフロップの出力を3段目以降
のフリップフロップリセット入力端子に接続したことを
特徴とする1秒タイマ。
Six flip-flops for frequency division are installed in series, and the fourth stage is
A first AND gate is provided that receives the outputs of the fifth and sixth stage flip-flops, and a second AND gate receives the outputs of the first NAND gate and the second stage flip-flop as inputs. An R-S flip-flop is provided in which the output of the second AND gate is connected to the reset input terminal, and the output of the second flip-flop is connected to the set input terminal. A one-second timer characterized in that it is connected to the flip-flop reset input terminal of the subsequent stages.
JP15034783U 1983-09-30 1983-09-30 1 second timer Pending JPS6059186U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15034783U JPS6059186U (en) 1983-09-30 1983-09-30 1 second timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15034783U JPS6059186U (en) 1983-09-30 1983-09-30 1 second timer

Publications (1)

Publication Number Publication Date
JPS6059186U true JPS6059186U (en) 1985-04-24

Family

ID=30333487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15034783U Pending JPS6059186U (en) 1983-09-30 1983-09-30 1 second timer

Country Status (1)

Country Link
JP (1) JPS6059186U (en)

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