JPS5921718U - Pulse number monitoring circuit - Google Patents
Pulse number monitoring circuitInfo
- Publication number
- JPS5921718U JPS5921718U JP11732882U JP11732882U JPS5921718U JP S5921718 U JPS5921718 U JP S5921718U JP 11732882 U JP11732882 U JP 11732882U JP 11732882 U JP11732882 U JP 11732882U JP S5921718 U JPS5921718 U JP S5921718U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- flip
- reset signal
- output
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Transmission And Conversion Of Sensor Element Output (AREA)
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案によるパルス数監視回路の一実施例を示
す回路図、第２図１−’−ｇは第１図に示す回路の各部
動作波形図である。
１〜３・・・第１〜第３フリツプフロツプ回路、４・・
・イニシャライズ回路、７・・・積分回路、１０・・・
ノアゲート、１１・・・オアゲート、１２・・・インバ
ータ、１３・・・トランジスタ。FIG. 1 is a circuit diagram showing an embodiment of a pulse number monitoring circuit according to the present invention, and FIG. 2 1-'-g are operational waveform diagrams of each part of the circuit shown in FIG. 1. 1 to 3...first to third flip-flop circuits, 4...
・Initialization circuit, 7... Integrating circuit, 10...
NOR gate, 11...OR gate, 12...inverter, 13...transistor.
Claims (1)
力とするとともに各り入力端が前段のセット出力端にそ
れぞれ接続され、かつ最前段のＤ入力端が電源に接続さ
れて直列接続構造とされ４二複数のフリップフロップ回
路と、電源出力を積分して積分出力信号を発生する積分
回路と、この積分回路から発生される積分出力信号のレ
ベルが予め定められた設定値に達した時にリセット信号
を発生して前記各フリップフロップ回路をリセットする
リセット信号発生回路と、このリセット信号および前記
フリップフロップ回路の最終段セット出力の発生時にオ
ンとなって前記積分回路をタリアするスイッチング素子
とを備え、前記積分回路の積分開始時からリセット信号
発生回路のリセット信号発生時点までの期間に直列接続
されたフリップフロップ回路の個数以上の入力パルス信
号が供給された時に最終段フリップフロップ回路のセッ
ト出力端から判別信号を発生することを特徴とするパル
ス数監視回路。The input pulse signals to be monitored are respectively used as clock inputs, and each input terminal is connected to the set output terminal of the preceding stage, and the D input terminal of the foremost stage is connected to the power supply to form a series connection structure. a flip-flop circuit, an integrating circuit that integrates the power supply output and generates an integral output signal, and generates a reset signal when the level of the integral output signal generated from this integrating circuit reaches a predetermined set value. a reset signal generating circuit for resetting each of the flip-flop circuits, and a switching element that is turned on and charges the integrating circuit when the reset signal and the final stage set output of the flip-flop circuit are generated; When input pulse signals equal to or greater than the number of flip-flop circuits connected in series are supplied during the period from the start of integration to the reset signal generation time of the reset signal generation circuit, a determination signal is output from the set output terminal of the final stage flip-flop circuit. A pulse number monitoring circuit characterized in that a pulse number is generated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11732882U JPS5921718U (en) | 1982-07-31 | 1982-07-31 | Pulse number monitoring circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11732882U JPS5921718U (en) | 1982-07-31 | 1982-07-31 | Pulse number monitoring circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5921718U true JPS5921718U (en) | 1984-02-09 |
Family
ID=30270130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11732882U Pending JPS5921718U (en) | 1982-07-31 | 1982-07-31 | Pulse number monitoring circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5921718U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01152523A (en) * | 1987-12-10 | 1989-06-15 | Nec Corp | Signal detecting circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5142382U (en) * | 1974-09-26 | 1976-03-29 | ||
| JPS528711A (en) * | 1975-07-09 | 1977-01-22 | Nippon Telegr & Teleph Corp <Ntt> | Dispersion-control electronic exchange system |
-
1982
- 1982-07-31 JP JP11732882U patent/JPS5921718U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5142382U (en) * | 1974-09-26 | 1976-03-29 | ||
| JPS528711A (en) * | 1975-07-09 | 1977-01-22 | Nippon Telegr & Teleph Corp <Ntt> | Dispersion-control electronic exchange system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01152523A (en) * | 1987-12-10 | 1989-06-15 | Nec Corp | Signal detecting circuit |
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