JPS58144926U - logic circuit - Google Patents
logic circuitInfo
- Publication number
- JPS58144926U JPS58144926U JP4059682U JP4059682U JPS58144926U JP S58144926 U JPS58144926 U JP S58144926U JP 4059682 U JP4059682 U JP 4059682U JP 4059682 U JP4059682 U JP 4059682U JP S58144926 U JPS58144926 U JP S58144926U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- outputs
- power supply
- supply voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の初期設定信号発生回路としての論理回路
を示す回路図、第２図は第１図のインバータの特性を示
す図、第３図ａ〜第３図Ｃは第１図の動作を説明するた
めの波形図、第４図は本考案に係る論理回路の一実施例
を示す回路図、第５図ａ′−第５図Ｃは第４図の動作を
説明するための波形図である。
１・・・基準電圧発生回路、２・・・デプリーション型
ＭＯ３）ランジスタ、３・・・エンハンスメント型ＭＯ
Ｓトランジスタ、４・・・基準電圧発生回路１の出力端
子、５・・・電源端子、６・・・インバータ、７・・・
初期設定信号発生回路、訃・・初期設定信号、９・・・
ナンド回路、１０・・・インバータ、１１・・・初期設
定信号、１２・・・パルス信号発生回路、１３・・・ナ
ンド回路、１４・・・インバータ、１５・・・初期設定
信号。Fig. 1 is a circuit diagram showing a logic circuit as a conventional initial setting signal generation circuit, Fig. 2 is a diagram showing the characteristics of the inverter shown in Fig. 1, and Figs. 3a to 3C show the operation of Fig. 1. FIG. 4 is a circuit diagram showing an embodiment of the logic circuit according to the present invention. FIGS. 5 a' to 5 C are waveform diagrams to explain the operation of FIG. 4. It is. 1... Reference voltage generation circuit, 2... Depletion type MO3) transistor, 3... Enhancement type MO
S transistor, 4... Output terminal of reference voltage generation circuit 1, 5... Power supply terminal, 6... Inverter, 7...
Initial setting signal generation circuit, initial setting signal, 9...
NAND circuit, 10... Inverter, 11... Initial setting signal, 12... Pulse signal generation circuit, 13... NAND circuit, 14... Inverter, 15... Initial setting signal.
Claims (1)
定となるまで発生する信号を第１の信号として出力する
回路と、基準電圧発生回路の出力基準電圧と制御システ
ムの電源電圧とを比較した結果発生する信号を第２の信
号として出力する回路と、この第２の信号を入力信号と
して一定時間幅の単一パルス信号を第３の信号として出
力する回路と前記第１の信号と第２の信号と第３の信号
とを入力とする３人力のナンド回路を有し、このナンド
回路の出力信号を制御システムの初期設定信号とするこ
とを特徴とする論理回路。A circuit that takes advantage of the change in power supply voltage when the power is turned on and outputs a signal that is generated until the power supply voltage becomes stable as the first signal, and a circuit that uses the output reference voltage of the reference voltage generation circuit and the power supply voltage of the control system. a circuit that outputs a signal generated as a result of comparing the signals as a second signal, a circuit that uses this second signal as an input signal and outputs a single pulse signal of a constant time width as a third signal, and the first signal. 1. A logic circuit comprising a three-man NAND circuit which receives as inputs a second signal and a third signal, and uses an output signal of the NAND circuit as an initial setting signal of a control system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4059682U JPS58144926U (en) | 1982-03-23 | 1982-03-23 | logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4059682U JPS58144926U (en) | 1982-03-23 | 1982-03-23 | logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58144926U true JPS58144926U (en) | 1983-09-29 |
Family
ID=30051805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4059682U Pending JPS58144926U (en) | 1982-03-23 | 1982-03-23 | logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58144926U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6238024A (en) * | 1985-08-12 | 1987-02-19 | Matsushita Electric Ind Co Ltd | Voltage detection circuit |
-
1982
- 1982-03-23 JP JP4059682U patent/JPS58144926U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6238024A (en) * | 1985-08-12 | 1987-02-19 | Matsushita Electric Ind Co Ltd | Voltage detection circuit |
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