JPH01100531U

JPH01100531U -

Info

Publication number: JPH01100531U
Application number: JP19584287U
Authority: JP
Priority date: 1987-12-25
Filing date: 1987-12-25
Publication date: 1989-07-06

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例の互いに逆相で非重
複なクロツク信号発生器回路図、第２図は第１図
の回路の動作タイミングチヤート、第３図および
第４図は互いに逆相で非重複なクロツク信号発生
器を使つたダイナミツク回路の実施例を示す図、
第５図は同相で非重複なクロツク信号発生器を使
用して、互いに逆相で非重複なクロツク信号で動
作するデジタルシステムを動作させる場合の実施
例を示す図である。１……入力線、２，３……クロツク出力線、４
……ナンド回路、５……ノア回路、６，７……反
転遅延回路、１０……逆相非重複クロツク信号発
生器、１１……Ｐチヤンネルトランジスタ、１２
……入力クロツク信号が高電圧レベルのときのデ
ータ出力を行う論理回路、１４……入力クロツク
信号が低電圧レベルのときのデータ出力を行う論
理回路、２０……同相非重複クロツク信号発生器
、２４……インバータ、２５……逆相非重複クロ
ツク信号で動作するデジタルシステム。 FIG. 1 is a circuit diagram of a non-overlapping clock signal generator with opposite phases to each other according to an embodiment of the present invention, FIG. 2 is an operation timing chart of the circuit shown in FIG. 1, and FIGS. A diagram illustrating an embodiment of a dynamic circuit using non-redundant clock signal generators in
FIG. 5 is a diagram illustrating an embodiment in which in-phase, non-overlapping clock signal generators are used to operate a digital system that operates with mutually opposite-phase, non-overlapping clock signals. 1...Input line, 2, 3...Clock output line, 4
... NAND circuit, 5 ... NOR circuit, 6, 7 ... Inverting delay circuit, 10 ... Negative phase non-overlapping clock signal generator, 11 ... P channel transistor, 12
...Logic circuit that outputs data when the input clock signal is at a high voltage level; 14...Logic circuit that outputs data when the input clock signal is at a low voltage level; 20...In-phase non-overlapping clock signal generator; 24...Inverter, 25...Digital system operating with anti-phase non-overlapping clock signals.

Claims

[Scope of utility model registration request]

It has one input terminal, and this input terminal is connected to one input terminal of a NAND circuit having two input terminals and one input terminal of a NOR circuit having two input terminals, and the output terminal of the NAND circuit is connected to one input terminal of a NAND circuit having two input terminals. The terminal is the first clock signal output terminal, and the NO
The output terminal of the R circuit is the output terminal of the second clock signal, and the other input terminal of the NAND circuit is
An inverted delayed signal of the output signal of the NOR circuit is input, and the other input terminal of the NOR circuit receives the NA signal.
A clock signal generator characterized in that it is configured to receive an inverted delayed signal of an output signal of an ND circuit.