JPS6193027U - - Google Patents

Info

Publication number
JPS6193027U
JPS6193027U JP17667484U JP17667484U JPS6193027U JP S6193027 U JPS6193027 U JP S6193027U JP 17667484 U JP17667484 U JP 17667484U JP 17667484 U JP17667484 U JP 17667484U JP S6193027 U JPS6193027 U JP S6193027U
Authority
JP
Japan
Prior art keywords
inverting
delay
circuit
inverting circuit
ecl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17667484U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17667484U priority Critical patent/JPS6193027U/ja
Publication of JPS6193027U publication Critical patent/JPS6193027U/ja
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す遅延回路に
よるスタート・ストツプ発振器の回路図、第2図
はその動作波形図、第3図は従来のスタート・ス
トツプ発振器の一例を示す回路図である。 図中、1,2はECL回路により構成されてい
る第1,第2の遅延回路、3はECL回路素子(
ノアゲート)、S,Sは第1、第2の可変電
流源を示す。
Fig. 1 is a circuit diagram of a start-stop oscillator using a delay circuit showing one embodiment of this invention, Fig. 2 is its operating waveform diagram, and Fig. 3 is a circuit diagram showing an example of a conventional start-stop oscillator. . In the figure, 1 and 2 are first and second delay circuits constituted by ECL circuits, and 3 is an ECL circuit element (
(Nor gate), S 1 and S 2 indicate first and second variable current sources.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ECLからなる反転回路の出力側に遅延用のコ
ンデンサを接続した第1、第2の遅延回路と、2
以上の入力端子を有する反転論理回路をループ状
に接続して発振回路を構成し、前記反転回路の出
力バツフアトランジスタに第1、第2の可変電流
源を接続したことを特徴とするスタート・ストツ
プ発振器。
first and second delay circuits each having a delay capacitor connected to the output side of an inverting circuit made of ECL;
An oscillation circuit is constructed by connecting inverting logic circuits having the above input terminals in a loop, and first and second variable current sources are connected to an output buffer transistor of the inverting circuit. stop oscillator.
JP17667484U 1984-11-22 1984-11-22 Pending JPS6193027U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17667484U JPS6193027U (en) 1984-11-22 1984-11-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17667484U JPS6193027U (en) 1984-11-22 1984-11-22

Publications (1)

Publication Number Publication Date
JPS6193027U true JPS6193027U (en) 1986-06-16

Family

ID=30734268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17667484U Pending JPS6193027U (en) 1984-11-22 1984-11-22

Country Status (1)

Country Link
JP (1) JPS6193027U (en)

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