JPS6451328U - - Google Patents
Info
- Publication number
- JPS6451328U JPS6451328U JP14630187U JP14630187U JPS6451328U JP S6451328 U JPS6451328 U JP S6451328U JP 14630187 U JP14630187 U JP 14630187U JP 14630187 U JP14630187 U JP 14630187U JP S6451328 U JPS6451328 U JP S6451328U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output terminal
- input terminal
- diagram
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
第１図及び第２図は夫々本考案回路の一実施例
の回路図及びその真理値タイミングチヤート、第
３図は一般の微分回路の動作タイミングチヤート
、第４図及び第５図は夫々本考案回路の他の実施
例の回路図及びその真理値タイミングチヤート、
第６図は第１図及び第７図に示す回路の等価ロジ
ツク図、第７図及び第８図は夫々従来回路の一例
の回路図及びその真理値タイミングチヤート、第
９図は第４図及び第１０図に示す回路の等価ロジ
ツク図、第１０図及び第１１図は夫々従来回路の
他の例の回路図及びその真理値タイミングチヤー
トである。
１，２……入力端子、３……出力端子、Ｑ１，
Ｑ２……トランジスタ、Ｃ１，Ｃ２……コンデン
サ、Ｒ１〜Ｒ４……抵抗。
1 and 2 are a circuit diagram and a truth value timing chart of an embodiment of the circuit of the present invention, respectively, FIG. 3 is an operation timing chart of a general differential circuit, and FIGS. 4 and 5 are respectively a diagram of an embodiment of the circuit of the present invention. A circuit diagram of another embodiment of the circuit and its truth value timing chart,
6 is an equivalent logic diagram of the circuits shown in FIGS. 1 and 7, FIGS. 7 and 8 are circuit diagrams of examples of conventional circuits and their truth timing charts, and FIG. 9 is an equivalent logic diagram of the circuits shown in FIGS. FIG. 10 is an equivalent logic diagram of the circuit shown in FIG. 10, and FIGS. 10 and 11 are circuit diagrams of other examples of the conventional circuit and truth value timing charts thereof, respectively. 1, 2...Input terminal, 3...Output terminal, Q1 ,
Q2 ...transistor, C1 , C2 ...capacitor, R1 to R4 ...resistance.
Claims (1)
端子との間に、微分回路を並列に接続してなる論
理回路。 A logic circuit consisting of a differentiating circuit connected in parallel between one input terminal and output terminal of an active switching element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14630187U JPS6451328U (en) | 1987-09-25 | 1987-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14630187U JPS6451328U (en) | 1987-09-25 | 1987-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6451328U true JPS6451328U (en) | 1989-03-30 |
Family
ID=31415658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14630187U Pending JPS6451328U (en) | 1987-09-25 | 1987-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6451328U (en) |
-
1987
- 1987-09-25 JP JP14630187U patent/JPS6451328U/ja active Pending
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