JPS6316713U - - Google Patents
Info
- Publication number
- JPS6316713U JPS6316713U JP11074886U JP11074886U JPS6316713U JP S6316713 U JPS6316713 U JP S6316713U JP 11074886 U JP11074886 U JP 11074886U JP 11074886 U JP11074886 U JP 11074886U JP S6316713 U JPS6316713 U JP S6316713U
- Authority
- JP
- Japan
- Prior art keywords
- output terminals
- graphic equalizer
- cascade
- regarded
- secondary bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図は、この考案の一実施例に係るグラフイ
ツクイコライザ回路を示すブロツク図である。第
２図は、２次バンプ特性を一般的に示す図である
。第３図は、２次バンプ特性を持つ回路の一例を
示す図である。第４図は、２次バンプ特性を持つ
回路の他の例を示す図である。第５図は、２次バ
ンプ特性の具体例を示す図である。第６図は、従
来のグラフイツクイコライザ回路の一例を示すブ
ロツク図である。第７図は、第６図のユニツト回
路の一例を示す図である。
６……実施例に係るグラフイツクイコライザ回
路、７……入力端、８１〜８ｎ……ユニツト回路
、９……出力端。
FIG. 1 is a block diagram showing a graphic equalizer circuit according to an embodiment of this invention. FIG. 2 is a diagram generally showing secondary bump characteristics. FIG. 3 is a diagram showing an example of a circuit having secondary bump characteristics. FIG. 4 is a diagram showing another example of a circuit having secondary bump characteristics. FIG. 5 is a diagram showing a specific example of secondary bump characteristics. FIG. 6 is a block diagram showing an example of a conventional graphic equalizer circuit. FIG. 7 is a diagram showing an example of the unit circuit of FIG. 6. 6... Graphic equalizer circuit according to the embodiment, 7... Input end, 81 to 8n... Unit circuit, 9... Output end.
Claims (1)
バンプ特性を持つユニツト回路を、入出力端間に
複数個縦続接続して成ることを特徴とするグラフ
イツクイコライザ回路。 A graphic equalizer circuit characterized in that a plurality of unit circuits having secondary bump characteristics whose circuit output terminals can be regarded as voltage sources are connected in cascade between input and output terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11074886U JPS6316713U (en) | 1986-07-19 | 1986-07-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11074886U JPS6316713U (en) | 1986-07-19 | 1986-07-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6316713U true JPS6316713U (en) | 1988-02-03 |
Family
ID=30990041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11074886U Pending JPS6316713U (en) | 1986-07-19 | 1986-07-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6316713U (en) |
-
1986
- 1986-07-19 JP JP11074886U patent/JPS6316713U/ja active Pending
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