JPS611931U - ECL circuit - Google Patents

ECL circuit

Info

Publication number
JPS611931U
JPS611931U JP8690984U JP8690984U JPS611931U JP S611931 U JPS611931 U JP S611931U JP 8690984 U JP8690984 U JP 8690984U JP 8690984 U JP8690984 U JP 8690984U JP S611931 U JPS611931 U JP S611931U
Authority
JP
Japan
Prior art keywords
ecl circuit
ecl
output
time
variable resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8690984U
Other languages
Japanese (ja)
Inventor
泉 古賀
敬司 常岡
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP8690984U priority Critical patent/JPS611931U/en
Publication of JPS611931U publication Critical patent/JPS611931U/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】 第1図は本考案に係るECL回路の一実施例を示す接続
図、第2図は第1図回路の人、出力特性説明図、第3図
は従来のECL回路の接続図、第4図は第3図の入・出
力特性説明図である。 U1・・・ECX8路、Q・・・トランジスタ、RL・
・・固定抵抗器、RV・・・可変抵抗器。
[Brief explanation of the drawings] Fig. 1 is a connection diagram showing an embodiment of the ECL circuit according to the present invention, Fig. 2 is a diagram showing the structure of the circuit shown in Fig. 1 and an illustration of output characteristics, and Fig. 3 is a conventional ECL circuit. FIG. 4 is an explanatory diagram of the input/output characteristics of FIG. 3. U1...ECX8 path, Q...transistor, RL.
...Fixed resistor, RV...Variable resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] その出力段がオープン・エミツタのトランジスタで構成
されたECL回路において、このECL回路の出力電流
を可変抵抗器を用いて可変させることにより、出力の立
下り時における動作時間を調整するようにしたことを特
徴とするECL回路。
In an ECL circuit whose output stage is composed of open-emitter transistors, the operating time at the time of output fall can be adjusted by varying the output current of the ECL circuit using a variable resistor. An ECL circuit featuring:
JP8690984U 1984-06-12 1984-06-12 ECL circuit Pending JPS611931U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8690984U JPS611931U (en) 1984-06-12 1984-06-12 ECL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8690984U JPS611931U (en) 1984-06-12 1984-06-12 ECL circuit

Publications (1)

Publication Number Publication Date
JPS611931U true JPS611931U (en) 1986-01-08

Family

ID=30638640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8690984U Pending JPS611931U (en) 1984-06-12 1984-06-12 ECL circuit

Country Status (1)

Country Link
JP (1) JPS611931U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5642038B2 (en) * 1972-02-28 1981-10-01

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5642038B2 (en) * 1972-02-28 1981-10-01

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