JPS6133515U - mixer bias circuit - Google Patents
mixer bias circuitInfo
- Publication number
- JPS6133515U JPS6133515U JP11471684U JP11471684U JPS6133515U JP S6133515 U JPS6133515 U JP S6133515U JP 11471684 U JP11471684 U JP 11471684U JP 11471684 U JP11471684 U JP 11471684U JP S6133515 U JPS6133515 U JP S6133515U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- mixer
- bias circuit
- follower
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【図面の簡単な説明】
第１区は従来のミキサバイアス回路を示すブロツク図、
第２図はこの考案のミキサバイアス回路を示すブロック
図である。
図において１は直流バイアス電源、１Ａは直流電源、２
は直流出力端子、３はミキサ、４はバイアス端子、５は
ＧＮＤ端子、６は抵抗、７は基準電源、８はボルテージ
フオロワ、９はエミツタフオロワである。
なお、図中同一符号は同一または相当部分を示す。[Brief explanation of the drawings] Section 1 is a block diagram showing a conventional mixer bias circuit;
FIG. 2 is a block diagram showing the mixer bias circuit of this invention. In the figure, 1 is a DC bias power supply, 1A is a DC power supply, and 2
3 is a DC output terminal, 3 is a mixer, 4 is a bias terminal, 5 is a GND terminal, 6 is a resistor, 7 is a reference power supply, 8 is a voltage follower, and 9 is an emitter follower. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ミキサと、上記直流電源とミ士サの間に直列に接続され
たエミツタフオロワと、このエミツタフオロワの入力端
に接続されたボルテージフオロワと、このボルテージフ
オロワの入力端に接続された基準電源と、前記ボルテー
ジフオロワの別の入力端に接続された抵抗とを備えたこ
とを特徴とするミキサバイアス回路。a DC power supply, a mixer connected to a DC output terminal of the DC power supply, an emitsuta follower connected in series between the DC power supply and the mixer, and a voltage follower connected to the input end of the emitsuta follower; A mixer bias circuit comprising: a reference power supply connected to an input end of the voltage follower; and a resistor connected to another input end of the voltage follower.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11471684U JPS6133515U (en) | 1984-07-27 | 1984-07-27 | mixer bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11471684U JPS6133515U (en) | 1984-07-27 | 1984-07-27 | mixer bias circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6133515U true JPS6133515U (en) | 1986-02-28 |
Family
ID=30673724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11471684U Pending JPS6133515U (en) | 1984-07-27 | 1984-07-27 | mixer bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6133515U (en) |
-
1984
- 1984-07-27 JP JP11471684U patent/JPS6133515U/en active Pending
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