JPS5850719U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS5850719U
JPS5850719U JP13999981U JP13999981U JPS5850719U JP S5850719 U JPS5850719 U JP S5850719U JP 13999981 U JP13999981 U JP 13999981U JP 13999981 U JP13999981 U JP 13999981U JP S5850719 U JPS5850719 U JP S5850719U
Authority
JP
Japan
Prior art keywords
muting
circuit
voltage
transistor
operated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13999981U
Other languages
Japanese (ja)
Inventor
小川 彰夫
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP13999981U priority Critical patent/JPS5850719U/en
Publication of JPS5850719U publication Critical patent/JPS5850719U/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図゛は従来のミューティング回路を示す回路図、第
2図は本考案のミューティング回路の一実施例を示す回
路図、第3図はミューティング回路のミューティング用
トランジスタの動作を説明する特性図、第4図なル1し
第6図は本考案のミューティング回路の他の実施例を示
す回路図である。 1・・・・・・電子回路、2.3・・・・・・コンデン
サ、4・・・・・・入力端子、5・・・・・・出力端子
、8・・・・・・入力端、9・・・・・・出力端、10
.11・・・・・・入力端子、Ql。 Q2・・・・・・トランジスタ、Dl、D2・・・・・
・ツェナーダイオード。
Fig. 1 is a circuit diagram showing a conventional muting circuit, Fig. 2 is a circuit diagram showing an embodiment of the muting circuit of the present invention, and Fig. 3 explains the operation of the muting transistor of the muting circuit. The characteristic diagrams shown in FIG. 4 and FIG. 6 are circuit diagrams showing other embodiments of the muting circuit of the present invention. 1...Electronic circuit, 2.3...Capacitor, 4...Input terminal, 5...Output terminal, 8...Input terminal , 9... Output end, 10
.. 11... Input terminal, Ql. Q2...Transistor, Dl, D2...
・Zener diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 1つの直流電源電圧によって動作しミューティングを必
要とする電子回路の入力もしくは出力端に前記電源電圧
より小さい直流電圧を出力させ、前記直流電圧を出力す
る前記電子回路の入力もしくは出力端とアース間にミュ
ーティング制御電圧によって動作するミューティング用
トランジスタ2を介挿してミューティング回路を形成し
、前記直流電源より大きなミューティング制御電圧によ
って前記ミューティング用トランジスタを動作させ、前
記直流電圧より小さなミューティング制御電圧によって
ミューティング用トランジスタを遮断するとともに、前
記ミューティジグ回路に前記直流電圧の安定化回路を挿
入してなることを特徴とするミューティング回路。
A DC voltage smaller than the power supply voltage is output to the input or output terminal of an electronic circuit that operates with one DC power supply voltage and requires muting, and between the input or output terminal of the electronic circuit that outputs the DC voltage and ground. A muting transistor 2 operated by a muting control voltage is inserted into the circuit to form a muting circuit, the muting transistor is operated by a muting control voltage greater than the DC power supply, and the muting transistor 2 is operated by a muting control voltage greater than the DC voltage. A muting circuit characterized in that a muting transistor is cut off by a control voltage, and the DC voltage stabilizing circuit is inserted into the muting circuit.
JP13999981U 1981-09-21 1981-09-21 Muting circuit Pending JPS5850719U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13999981U JPS5850719U (en) 1981-09-21 1981-09-21 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13999981U JPS5850719U (en) 1981-09-21 1981-09-21 Muting circuit

Publications (1)

Publication Number Publication Date
JPS5850719U true JPS5850719U (en) 1983-04-06

Family

ID=29933174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13999981U Pending JPS5850719U (en) 1981-09-21 1981-09-21 Muting circuit

Country Status (1)

Country Link
JP (1) JPS5850719U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155898U (en) * 1981-03-24 1982-09-30

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155898U (en) * 1981-03-24 1982-09-30
JPH0224312Y2 (en) * 1981-03-24 1990-07-03

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