JPS6183342U - - Google Patents

Info

Publication number
JPS6183342U
JPS6183342U JP16870784U JP16870784U JPS6183342U JP S6183342 U JPS6183342 U JP S6183342U JP 16870784 U JP16870784 U JP 16870784U JP 16870784 U JP16870784 U JP 16870784U JP S6183342 U JPS6183342 U JP S6183342U
Authority
JP
Japan
Prior art keywords
transistor
power supply
resistor
emitter
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16870784U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16870784U priority Critical patent/JPS6183342U/ja
Publication of JPS6183342U publication Critical patent/JPS6183342U/ja
Pending legal-status Critical Current

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  • Electronic Switches (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案のスイツチ回路の一実施例を
示す図、第2図は従来のスイツチ回路を示す図で
ある。 図において、1はトランジスタ、2は信号入力
端子、3は制御端子、4は出力信号端子、5は抵
抗器、6は電源、7は1と極性が逆なトランジス
タ、8は抵抗器である。なお、図中同一あるいは
相当部分には同一符号を付して示してある。
FIG. 1 is a diagram showing an embodiment of the switch circuit of this invention, and FIG. 2 is a diagram showing a conventional switch circuit. In the figure, 1 is a transistor, 2 is a signal input terminal, 3 is a control terminal, 4 is an output signal terminal, 5 is a resistor, 6 is a power supply, 7 is a transistor whose polarity is opposite to 1, and 8 is a resistor. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] コレクタを第1の電源に接続した第1のトラン
ジスタのエミツタと第2のトランジスタのコレク
タとを接続した組トランジスタを複数組用い、第
2のトランジスタのエミツタを相互に接続し、そ
のエミツタから第2の電源へ抵抗器を介して接続
し、また第1および第2のトランジスタと極性が
逆な第3のトランジスタのベースを接続し、その
第3のトランジスタのコレクタを第2の電源へ、
またエミツタを抵抗器を介して第1の電源に接続
し、各組トランジスタの第1のトランジスタのベ
ースを制御端子とし、第2のトランジスタのベー
スを信号入力端子とし、第3のトランジスタのエ
ミツタを出力端子とすることを特徴とするスイツ
チ回路。
A plurality of sets of transistors are used in which the emitter of a first transistor whose collector is connected to a first power supply is connected to the collector of a second transistor, the emitters of the second transistors are connected to each other, and the emitters of the second transistor are connected to each other. connecting the base of a third transistor having opposite polarity to the first and second transistors to the power supply of the transistor via a resistor, and connecting the collector of the third transistor to the second power supply;
In addition, the emitter is connected to the first power supply via a resistor, the base of the first transistor of each transistor group is used as a control terminal, the base of the second transistor is used as a signal input terminal, and the emitter of the third transistor is connected to the first power supply through a resistor. A switch circuit characterized by having an output terminal.
JP16870784U 1984-11-07 1984-11-07 Pending JPS6183342U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16870784U JPS6183342U (en) 1984-11-07 1984-11-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16870784U JPS6183342U (en) 1984-11-07 1984-11-07

Publications (1)

Publication Number Publication Date
JPS6183342U true JPS6183342U (en) 1986-06-02

Family

ID=30726468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16870784U Pending JPS6183342U (en) 1984-11-07 1984-11-07

Country Status (1)

Country Link
JP (1) JPS6183342U (en)

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