JPS6421518U - - Google Patents

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Publication number
JPS6421518U
JPS6421518U JP11448587U JP11448587U JPS6421518U JP S6421518 U JPS6421518 U JP S6421518U JP 11448587 U JP11448587 U JP 11448587U JP 11448587 U JP11448587 U JP 11448587U JP S6421518 U JPS6421518 U JP S6421518U
Authority
JP
Japan
Prior art keywords
differential amplifier
sets
amplifier circuits
transistors
emitters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11448587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11448587U priority Critical patent/JPS6421518U/ja
Publication of JPS6421518U publication Critical patent/JPS6421518U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の回路図、第２図は
第１図の等価回路図、第３図、第４図は夫々本考
案の他の実施例の回路図、第５図は従来の差動増
幅回路の回路図である。 Ｑ１〜Ｑ１０……トランジスタ、Ｒｅ，Ｒｅ１
〜Ｒｅ３……抵抗、Ｉ１〜Ｉ５……電流源、Ａ１
，Ａ２，Ｂ１，Ｂ２……入力端子。 Figure 1 is a circuit diagram of one embodiment of the present invention, Figure 2 is an equivalent circuit diagram of Figure 1, Figures 3 and 4 are circuit diagrams of other embodiments of the present invention, and Figure 5 is an equivalent circuit diagram of Figure 1. FIG. 2 is a circuit diagram of a conventional differential amplifier circuit. Q 1 to Q 10 ...transistor, Re, Re 1
 ~ Re3 ...Resistance, I1 ~ I5 ...Current source, A1
 , A 2 , B 1 , B 2 ...input terminals.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 夫々が２つのトランジスタを有する２組の差動
増幅回路からなり、これら２組の差動増幅回路間
の対応するトランジスタのコレクタとベースとに
夫々共通の信号が与えられるように接続する一方
、前記２組の少なくとも一方の差動増幅回路にて
２つのトランジスタのエミツタを抵抗を介して接
続したことを特徴とする差動増幅装置。 It consists of two sets of differential amplifier circuits each having two transistors, and is connected so that a common signal is applied to the collector and base of the corresponding transistor between these two sets of differential amplifier circuits, respectively. 1. A differential amplifier device, characterized in that the emitters of two transistors in at least one of two sets of differential amplifier circuits are connected via a resistor.
JP11448587U 1987-07-28 1987-07-28 Pending JPS6421518U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11448587U JPS6421518U (en) 1987-07-28 1987-07-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11448587U JPS6421518U (en) 1987-07-28 1987-07-28

Publications (1)

Publication Number Publication Date
JPS6421518U true JPS6421518U (en) 1989-02-02

Family

ID=31355277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11448587U Pending JPS6421518U (en) 1987-07-28 1987-07-28

Country Status (1)

Country Link
JP (1) JPS6421518U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03156280A (en) * 1989-11-10 1991-07-04 Sanyo Electric Co Ltd Microwave drier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03156280A (en) * 1989-11-10 1991-07-04 Sanyo Electric Co Ltd Microwave drier
JPH0765844B2 (en) * 1989-11-10 1995-07-19 三洋電機株式会社 Microwave dryer

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